Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-12-30
2002-02-26
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S368000, C257S380000, C257S069000, C257S369000
Reexamination Certificate
active
06351015
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a transistor device of MOS structure, a method for manufacturing the same, a transistor circuit of CMOS structure and an integrated circuit device having an output buffer.
2. Description of the Related Art
Now, various integrated circuit devices are used for various data processes. For example, there is an integrated circuit device in which interface is quickly carried out. Such an integrated circuit device is formed as structure in which a terminating resistor is connected to an output buffer of a quick interface. The output buffer is typically provided with a transistor circuit of CMOS structure.
A first conventional example of such a transistor circuit will be described below with reference to FIG.
1
.
FIG. 1
is a plan view showing the transistor circuit. Here, a transistor circuit
10
exemplified as the first conventional example is formed in the CMOS structure, and provided with a pair of transistor devices
11
,
12
of the MOS structure in which conductive types are opposite to each other.
The pair of transistor devices
11
,
12
have source electrodes
13
,
14
, drain electrodes
15
,
16
, gate electrodes
17
,
18
and diffusion regions
19
,
20
, respectively. The source electrodes
13
,
14
are opposite to the drain electrodes
15
,
16
through the gate electrodes
17
,
18
at the positions of the diffusion regions
19
,
20
, respectively.
A pair of gate electrodes
17
,
18
are formed as a single piece, and commonly connected to one input terminal
21
. A pair of drain electrodes
15
,
16
are also formed as a single piece, and commonly connected to one output terminal
22
. A pair of source electrodes
13
,
14
are respectively connected to a pair of power supply terminals
23
,
24
.
The transistor circuit
10
having the above-mentioned structure can be used as an output buffer of a quick interface. In this case, an output terminal of a semiconductor circuit (not shown) is connected to the input terminal
21
of the transistor circuit
10
. A terminating resistor (not shown) is connected to the output terminal
22
of the transistor circuit
10
.
However, if an integrated circuit device having the above-mentioned structure is formed, the transistor circuit
10
and the terminating resistor are actually connected with each other through a transmission line. For this reason, if a transmission impedance of the transmission line and an output impedance of the transistor circuit
10
do not match with each other, various troubles occur, such as difficulty in quick transmission of the quick interface due to the occurrence of reflection noise and the like.
So, in an actual integrated circuit device, the transistor circuit
10
is designed such that if the transmission impedance of the transmission line connected to the output buffer (the transistor circuit
10
) is known in advance, the output impedance of the output buffer is adapted to be matched with the transmission impedance. If the output impedance of the transistor circuit
10
and the transmission impedance of the transmission line match with each other as mentioned above, this method can protect the various troubles, such as the occurrence of the reflection noise and the like, to thereby improve the performance of the integrated circuit device.
As mentioned above, the various troubles in the integrated circuit device can be protected if the output impedance of the transistor circuit
10
is adapted to be matched with the transmission impedance of the transmission line.
However, the output impedance of the transistor circuit
10
is an impedance in the conductive section from the power supply terminals
23
,
24
to the output terminal
22
when the gate electrodes
17
,
18
are turned on. Thus, the output impedance of the transistor circuit
10
depends on the gate lengths which are layer widths of the gate electrodes
17
,
18
.
For this reason, if the gate lengths of the gate electrodes
17
,
18
are varied because of manufacturing error, the output impedance of the transistor circuit
10
is also varied to thereby bring about the various troubles in the integrated circuit device. Especially, the gate lengths of the gate electrodes
17
,
18
tend to be shortened in order to make the circuit highly integrated and reduce a consumption power in recent years. Hence, the affection of the variation in the gate length resulting from the manufacturing error becomes very serious.
Such as a transistor circuit
30
exemplified as a second conventional example in
FIG. 2
, there is also a product in which various electrodes
33
to
38
of transistor devices
31
,
32
and diffusion regions
39
,
40
are extended in a direction orthogonal to a gate length (a direction of a gate width) to relatively suppress the variation of an output impedance resulting from a variation of the gate length.
Here, the transistor circuit
30
is formed in CMOS structure and provided with a pair of transistor devices
31
,
32
of MOS structure in which conductive types are opposite to each other.
The pair of transistor devices
31
,
32
have source electrodes
33
,
34
, drain electrodes
35
,
36
, gate electrodes
37
,
38
and diffusion regions
39
,
40
, respectively. The source electrodes
33
,
34
are respectively opposite to the drain electrodes
35
,
36
through the gate electrodes
37
,
38
at the positions of the diffusion regions
39
,
40
, respectively.
A pair of gate electrodes
37
,
38
are formed as a single piece, and commonly connected to one input terminal
21
. A pair of drain electrodes
15
,
16
are also formed as a single piece, and commonly connected to one output terminal
22
. A pair of source electrodes
33
,
34
are respectively connected to a pair of power supply terminals
23
,
24
.
For example, if the gate width is extended by N times, a variation of an output impedance resulting from the extension is 1/N. Nevertheless, the variation of the output impedance is still caused by the variation of the gate width. Moreover, if the various electrodes
33
to
38
and the diffusion regions
39
,
40
are extended by several times as mentioned above, the integration degree of the transistor circuit
30
and the response thereof are dropped, and the consumption power is increased.
So, in an integrated circuit device employing an SSTL (Stub Series—Terminated Logic) manner as a quick interface and the like, the following method is proposed. That is a method for connecting a resistance element in series to an output terminal of an output buffer, and then connecting the output terminal of the output buffer to a transmission line through the resistance element to match an impedance of the output buffer with the resistance element to that of the transmission line. However, in this method, circuit elements are increased to thereby reduce the integration degree of the integrated circuit device and the productivity thereof. Thus, an operational speed of the quick interface is also impeded.
Japanese Laid Open Patent Application (JP-A-Heisei 9-8286) discloses a field effect transistor as described below. An impedance converter is mounted between a gate electrode terminal and a gate electrode. Thus, this method can suppress the impedance mismatch between a first transmission line on which an input signal is transmitted and a second transmission line provided with a source electrode and the gate electrode. Moreover, a resistor whose value is defined so as to agree with a characteristic impedance of the second transmission line provided with the gate electrode and the source electrode is connected between the gate electrode and the source electrode. Hence, the second transmission line is terminated to thereby suppress the reflection of a transmission signal.
Japanese Laid Open Patent Application (JP-A-Heisei 9-283710) discloses a gate bias circuit of FET as described below. A signal through an input terminal and an impedance matching circuit is sent to a gate of the FET. A bias resistor and a bias adjustment circuit de
Flynn Nathan
Quinto Kevin
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