Transistor device layout

Details Transistor device layout Transistor device layout

1992-11-30

1994-05-24

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For high frequency device

257717, 257724, 257691, 257584, H01L 2302, H01L 2312, H01L 2348, H01L 2940

Patent

active

053151569

ABSTRACT:
A modified transistor layout allows operation at high frequencies without adversely effecting transistor power gain. The base and collector circuits are modified in order to minimize ground bar resistance and feedback problems between the input and output circuits. This reduces the applied negative feedback and maximizes gain. The collector contact bar and the output capacitor are mounted directly on the collector island such that the output capacitor is wired directly to the grounded package metal and the collector is wired to the collector contact bar. This eliminates the need to wirebond to areas on the collector island that are covered with the eutectic run-out which results from mounting the transistor chip on the collector island.

REFERENCES:
patent: 3860879 (1975-01-01), McQuiddy, Jr. et al.
patent: 3886505 (1975-05-01), Jacobson
patent: 3969752 (1976-07-01), Martin et al.
patent: 4168507 (1979-09-01), Yester, Jr.
patent: 4200880 (1980-04-01), Frey
patent: 4891686 (1990-01-01), Krausse, III

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