Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2001-12-14
2004-05-04
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S299000, C438S301000, C438S303000, C438S529000
Reexamination Certificate
active
06730582
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to electronic circuits and are more particularly directed to a metal oxide semiconductor (“MOS”) transistor having a configuration for enhanced electrostatic discharge (“ESD”) protection.
Many contemporary integrated circuits include two sets of transistors, where a first transistor set operates at a first operating voltage while a second transistor set operates at a second and different operating voltage. For example, in various modem circuits a first voltage is used for transistors implemented at the input/output (“I/O”) level while a second and lower voltage is used for transistors implemented in the operational core of the circuit. In these cases, transistors suitable for use at the higher I/O voltages are required and, thus, the design of such transistors must take this factor into account.
In addition to having a higher operating voltage, typically the I/O transistors are more susceptible to ESD as opposed to the core transistors because the former generally isolate the latter from external power effects. ESD occurs due to a relatively short period of relatively high voltage or current imposed on a device. For example, ESD can be caused by the human body, by poorly grounded machinery such as test equipment, or in electrically noisy environments as may be incurred in automotive applications or in consumer applications, including computers. Moreover, various testing has been developed to ensure that certain circuits comply with ESD standards, such as a test circuit mandated by MIL-STD 883B. In any event, due to the risk of ESD, devices are often engineered and tested to ensure that they can withstand certain levels of ESD.
By way of further background to the type of transistors used both in I/O and core locations of prior art circuits,
FIG. 1
a
illustrates a cross-sectional view of a prior art MOS transistor
10
which, by way of example, is an n-channel (NMOS) transistor. Transistor
10
is formed using a substrate
20
which, in the example of
FIG. 1
a
, is formed from a p-type semiconductor material and is therefore labeled with a “P” designation. Two shallow trench isolation (“STI”) regions
22
1
, and
22
2
are formed in substrate
20
and may be various insulating materials such as silicon oxide or silicon nitride. A gate dielectric
24
is formed over substrate
20
, and it may be an oxide, a thermally grown silicon dioxide, a nitride, an oxynitride, or a combination of these or other insulators. A gate conductor
26
is formed over gate dielectric
24
, such as by forming a layer of material which is patterned and etched to form gate conductor
26
. Further, gate conductor
26
is typically formed from polysilicon, although other materials may be used. For the sake of reference, gate conductor
26
is also shown by a schematic indication in
FIG. 1
a
with the identifier “G
1
.” Two lightly doped diffused regions
28
1
and
28
2
are formed within substrate
20
and are self-aligned with respect to the sidewalls of gate conductor
26
and also extend slighty under gate conductor
26
. In the present example, lightly doped diffused regions
28
1
and
28
2
are n-type regions. Thereafter, sidewall insulators
30
1
and
30
2
are formed along the sidewalls of gate conductor
26
. Next, doped regions
32
1
and
32
2
are formed within substrate
20
and are self-aligned with respect to sidewall insulators
30
1
and
30
2
, respectively. Doped regions
32
1
and
32
2
are formed using the same type of conductivity implant as lightly doped diffused regions
28
1
and
28
2
, but typically with a greater concentration of those dopants and/or using a greater implant energy as compared to that used to form lightly doped diffused regions
28
1
and
28
2
. Each of doped regions
32
1
and
32
2
combines with a corresponding one of lightly doped diffused regions
28
1
and
28
2
to form what are generally structurally identical and symmetric regions relative to gate conductor
26
; thus, these regions are sometimes referred to as source/drain regions. However, for the sake of reference, in
FIG. 1
a
the combination of region
28
1
and region
32
1
is considered to provide the source of transistor
10
and is schematically labeled “S
1
”, and the combination of region
28
2
and region
32
2
is considered to provide the drain of transistor
10
and is schematically labeled “D
1
.”
The operation of transistor
10
is well known in the art and, thus, the following discussion only addresses aspects relating to observations by the present inventors and as improved upon by the preferred embodiments discussed later. Under normal operation, when a proper gate-to-source potential is applied to transistor
10
, then current conducts between source S
1
and drain D
1
. As appreciated from
FIG. 1
a
, this current path is between the inward boundaries of lightly doped diffused regions
28
1
and
28
2
and below gate dielectric
24
, and this area is known as the transistor channel.
To further illustrate the operation of transistor
10
and particularly to illustrate an aspect during an ESD event,
FIG. 1
b
illustrates a plan view of various components of transistor
10
. Generally,
FIG. 1
b
illustrates the source S
1
, gate G
1
, and drain D
1
of transistor
10
. Further, the channel spans between two dashed lines, where those lines are intended to illustrate the inward boundaries of lightly doped diffused regions
28
1
and
28
2
as they exist below gate G
1
. Given the location of the channel, current under normal operation travels uniformly in the horizontal dimension relative to
FIG. 1
b
(and
FIG. 1
a
). However, under ESD events, it has been observed that there may be an area of so-called runaway current, that is, a particular physical location within the channel where a considerably greater amount of current passes as opposed to other locations within the channel. Such a physical location is referred to as a “filament” and, for sake of illustration, one such filament is shown by way of a bi-directional arrow designated F
1
in
FIG. 1
b
. Moreover, an ESD event may cause damage to transistor
10
because most of the energy passes by way of filament F
1
, thereby posing the greatest potential for device damage along the path of that filament.
In view of the above, there arises a need to improve upon the prior art as is achieved by the preferred embodiments described below.
BRIEF SUMMARY OF THE INVENTION
In the preferred embodiment, there is a method of forming a transistor in a semiconductor active area. The method forms a gate structure in a fixed relationship to the semiconductor active area thereby defining a first source/drain region adjacent a first structure sidewall and a second source/drain region adjacent a second gate sidewall. The method also forms a lightly doped diffused region formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure. Other aspects are also disclosed and claimed.
REFERENCES:
patent: 5019888 (1991-05-01), Scott et al.
patent: 5238859 (1993-08-01), Kamijo et al.
patent: 5246872 (1993-09-01), Mortensen
patent: 5508212 (1996-04-01), Wang et al.
patent: 5675168 (1997-10-01), Yamashita et al.
patent: 6013570 (2000-01-01), Yu et al.
patent: 6215156 (2001-04-01), Yang
patent: 2002/0019104 (2002-02-01), Miyagi
patent: 8-172135 (1996-07-01), None
JP 8-172135 English Language Abstract (Miyagi) Jul. 2,1996, [online], [retrieved on Nov. 13, 2002] Retrieved from the Industrial Property Digital Library of the Japanese Patent Office using internet <URL: http://www.ipdl.jpo.go.jp/homepg_e.ipdl>.
Brady III W. James
McLarty Peter K.
Vockrodt Jeff
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