Transistor array and semiconductor memory configuration...

Details Transistor array and semiconductor memory configuration... Transistor array and semiconductor memory configuration...

2005-01-04

2005-01-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S304000

Reexamination Certificate

active

06838724

ABSTRACT:
A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

REFERENCES:
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patent: 6344390 (2002-02-01), Bostelmann et al.
patent: 6515327 (2003-02-01), King
patent: 20020127796 (2002-09-01), Hofmann et al.
patent: 20020127803 (2002-09-01), Schlosser et al.
patent: 101 11 755 (2002-05-01), None
patent: 101 25 967 (2002-07-01), None
patent: 101 11 760 (2002-10-01), None

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