Transistor and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257328, 257378, 257401, 438156, 438212, 438234, 438268, 438585, H01L 2972

Patent

active

060085185

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to a transistor and a method of fabricating the same, and more particularly, it relates to an improvement for compatibly improving an output characteristic and an OFF characteristic.
2. Discussion of the Background
In general, a MOSFET (hereinafter simply referred to as MOS) has been mainly employed in a region having a rated voltage of not more than 200 V and a bipolar transistor (hereinafter simply referred to as BIP) or an insulated gate bipolar transistor (hereinafter simply referred to as IGBT) has been employed in a region of at least 300 V in various types of power transistors (power transistors). The respective ones of the conventional MOS, BIP and IGBT are now described.
FIG. 37 is a sectional view showing the structure of the conventional MOS. This MOS 151 corresponds to an example of the so-called vertical MOS. As shown in FIG. 37, an n.sup.- layer 172 is formed on an N.sup.+ layer 171 in the MOS 151, and p-type base layers 173 are selectively formed in an upper surface part of the n.sup.- layer 172 by diffusing a p-type impurity. Further, n-type source regions 174 are selectively formed in upper surface parts of the base layers 173 by diffusing an n-type impurity. The source layers 174 are partially arranged in single base layers 173, and the impurity concentrations thereof are set higher than the n.sup.- layer 172.
A gate oxide film 177 is formed on an exposed surface of the n.sup.- layer 172 and exposed surfaces of the base layers 173 held between the n.sup.- layer 172 and the source layers 174, and a gate electrode 178 made of polysilicon is formed further on this gate oxide film 177. Parts of the base layers 173 opposed to the gate electrode 178 through the gate oxide film 177 function as channel regions 176.
A source electrode 180 is formed on the exposed surfaces of the base layers 173 excluding the channel regions 176, i.e., upper surfaces of regions held between the source layers 174. The source electrode 180 and the gate electrode 178 are typically isolated from each other by an interlayer isolation film 179. Further, a drain electrode 182 is formed on an exposed surface of the N.sup.+ layer 171. These source electrode 180 and drain electrode 182 form a pair of main electrodes functioning as paths of a main current.
This MOS 51 operates as follows: First, a drain voltage V.sub.DS of prescribed magnitude is applied between the drain electrode 182 and the source electrode 180, so that the side of the drain electrode 182 is positive. When applying a gate voltage V.sub.GE (i.e., turning on a gate) exceeding a gate threshold voltage V.sub.GE (th) between the gate electrode 178 and the source electrode 180 so that the side of the gate electrode 178 is positive in this state, the p-type channel regions 176 are inverted to an n type and n-type channels are formed in the channel regions 176. Consequently, the n.sup.- layer 172 and the source layers 174 conduct with each other, whereby the drain electrode 182 and the source electrode 180 conduct with each other. Namely, the MOS 151 enters an ON state.
Then, when inverting the gate voltage V.sub.GE from the positive value to the value of zero or a negative (reverse bias) value (i.e., turning off the gate) in the state applying the drain voltage V.sub.DS, the channel regions 176 having been inverted to the n type return to the original p type. Consequently, the n.sup.- layer 172 and the source layers 174 are disconnected from each other, whereby the drain electrode 182 and the source electrode 180 are disconnected from each other. Namely, the MOS 151 enters an OFF state.
FIG. 38 is a sectional view showing the structure of the conventional BIP. In this BIP 152, an n.sup.- layer 202 is formed on an N.sup.+ layer 201, and a p-type base layer 203 is formed on an upper surface of the n.sup.- layer 202 by diffusing a p-type impurity. Further, an n-type emitter layer 204 is selectively formed in an upper surface part of the base layer 203 by diffusing an n-type impurity

REFERENCES:
patent: 5751024 (1998-05-01), Takahashi

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