Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-01-02
2004-09-21
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S303000
Reexamination Certificate
active
06794714
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an improved transistor and a method for fabricating the same that can improve electrical properties and manufacturing yield. The method disclosed includes forming a device isolation oxide film, etching the isolation oxide to form an active region, and forming a gate electrode within the active region.
2. Description of the Background Art
FIGS. 1
to
3
respectively illustrate a conventional transistor. Here,
FIG. 1
is a layout diagram illustrating the transistor,
FIG. 2
is a cross-sectional diagram illustrating the transistor, taken along line I—I in
FIG. 1
, and
FIG. 3
is a cross-sectional diagram illustrating the transistor, taken along line II—II in FIG.
1
.
As illustrated therein, the conventional transistor includes: a device isolation oxide film
14
formed in a device isolation region on a p-type semiconductor substrate
11
; a gate electrode
16
formed by positioning a gate oxide film
15
on the semiconductor substrate
11
; a lightly doped drain (LDD) region
17
formed in the active region on the semiconductor substrate
11
at both sides of the gate electrode
16
; a second nitride film spacer
18
formed at both sides of the gate electrode
16
; and a source/drain junction region
19
formed at both sides of the second nitride film spacer
18
and the gate electrode
16
.
FIGS. 4
a
to
4
d
and
5
a
to
5
d
are cross-sectional diagrams illustrating sequential steps of a conventional method for fabricating the transistor.
Referring to
FIGS. 4
a
and
5
a
, a device isolation region is defined according to a general shallow trench isolation (STI) method. A pad oxide film
12
, a first nitride film
13
and a first photoresist film pattern are sequentially formed on the p-type semiconductor substrate
11
. Here, the first photoresist film pattern is formed according to conventional exposure and development processes employing a device isolation mask.
Thereafter, the first nitride film
13
, pad oxide film
12
and a portion of semiconductor substrate
11
are selectively etched using the first photoresist pattern as a mask to form a trench.
The first photoresist film pattern is removed, and the device isolation oxide film
14
is grown on the whole surface including the trench and then planarized utilizing a chemical mechanical polishing (CMP) or etchback process. The planarization process uses first nitride film
13
as planarization end point with sufficient overetch to ensure that the device isolation oxide film
14
remains only in the trench.
As illustrated in
FIGS. 4
b
and
5
b
, a channel region (C) is formed on the semiconductor substrate
11
by removing the nitride film
13
and the pad oxide film
12
from the active area of semiconductor substrate
11
, and implanting ions into the semiconductor substrate
11
.
The gate oxide film
15
is then formed on the semiconductor substrate
11
utilizing a thermal oxidation process, and the gate electrode
16
, preferably having a stacked structure with a polysilicon layer
16
a
and a tungsten layer
16
b
, is then formed on the gate oxide film
15
.
A second photoresist film pattern is then formed on the tungsten layer
16
b
. Here, the photoresist film pattern is formed utilizing conventional exposure and development processes and a gate electrode mask.
The tungsten layer
16
b
, polysilicon layer
16
a
and gate oxide film
15
are then selectively etched using the second photoresist film pattern as a mask to form the gate electrode
16
. The second photoresist film pattern is then removed.
As depicted in
FIGS. 4
c
and
5
c
, a lightly doped n-type impurity ion implantation process is then performed using the gate electrode
16
as a mask. The implanted ions are then diffused using a drive-in process to form a lightly-doped drain region
17
on both sides of the gate electrode
16
.
As shown in
FIGS. 4
d
and
5
d
, the second nitride film is then formed on the whole surface including the gate electrode
16
. The second nitride film spacer
18
is formed on the semiconductor substrate
11
at both sides of the gate electrode
16
, by etching the second nitride film.
A highly doped n-type impurity ion implantation process is then performed using the gate electrode
16
and the second nitride film spacer
18
as a mask. The ions are diffused using drive-in process, thereby forming a source/drain junction region
19
at both sides of the gate electrode
16
including the second nitride film spacer
18
.
However, the conventional transistor and the method for fabricating the same have the following disadvantages:
Firstly, the sidewalls of the device isolation oxide film are commonly damaged during the LOCOS process, STI process, ion implantation process and succeeding thermal treatment. Thus, a leakage current increases and the refresh properties of the DRAM deteriorate.
Secondly, the thickness of the gate oxide film may be smaller at the end portion of the active region than the center portion thereof because of a stepped portion from the device isolation oxide film. Accordingly, gate oxide integrity is damaged and a reverse narrow width effect is generated in the transistor. In phenomenon known as the “reverse narrow width effect”, V
T
(threshold voltage) is lowered, breakdown voltage is reduced, and as a result, junction leakage current is increased.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a transistor that can prevent or suppress leakage currents, damage to the gate oxide integrity, and reverse narrow width effect, and a method for fabricating the same.
In order to achieve the above-described object of the present invention, there is provided a transistor: a device isolation oxide film that defines an active region on a semiconductor substrate. A gate electrode is provided in the active region with a gate oxide film positioned between the substrate and the gate electrode, the gate electrode having a stacked structure. The first gate electrode layer is approximately equal height to the height of the device isolation oxide film. A second gate electrode layer is subsequently formed on the upper portion of the gate electrode. A lightly doped drain (LDD) region provided in the active region at both sides of the gate electrode with a nitride film spacer positioned at the sidewalls of the device isolation oxide film and the gate electrode layer. A source/drain junction region is provided in the active region on both sides of the gate electrode with second and third oxide films filling in the active region between the first gate electrode and the device isolation oxide film.
There is also provided a method for fabricating a transistor, including the steps of: forming a device isolation oxide film to define an active region at the upper portion of a semiconductor substrate; forming a first gate electrode on a gate oxide film in the active region; forming a first oxide film on the surface of the first gate electrode; forming a lightly doped drain (LDD) region in the active region at both sides of the first gate electrode; forming an insulation film spacer at both sides of the first gate electrode and at the sidewalls of the device isolation film; forming a source/drain junction region on the semiconductor substrate at both sides of the first gate electrode including the insulation film spacer; forming second and third planarized oxide films between the first gate electrode including the insulation film spacer and the device isolation oxide film; and forming a gate electrode having a stacked structure with a first gate electrode, a second gate electrode and a hard mask layer.
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patent: 6017784 (2000-01-01), Ohta et al.
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patent: 6063680 (2000-05-01), Wu
patent: 6072241 (2000-06-01), Kojima
patent: 6074921 (2000-06-01), Lin
patent: 6077748 (2000-06-01), Gardner et al.
patent: 6180475 (2001-01-01), Cheek et al.
patent: 6194299 (2
Hyundai Electronics Industries Co,. Ltd.
Nelms David
Pillsbury & Winthrop LLP
Vu David
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