Transistor and memory cell array

Details Transistor and memory cell array Transistor and memory cell array

2011-06-07

2011-06-07

Bryant, Kiesha R (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Charge transfer device

C257S242000, C257SE27060, C438S272000, C438S282000

Reexamination Certificate

active

07956387

ABSTRACT:
A transistor, which is formed in a semiconductor substrate having a top surface, includes first and second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode for controlling an electrical current flowing in the channel. The gate electrode is disposed in a lower portion of a gate groove defined in the top surface of the semiconductor substrate. The upper portion of the groove is filled with an insulating material. The channel includes a fin-like portion in the shape of a ridge having a top side and two lateral sides in a cross-section perpendicular to a direction defined by a line connecting the first and second source/drain regions. The gate electrode encloses the channel at the top side and the two lateral sides thereof.

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Office Action issued by the Korean Patent Office in counterpart Korean Patent Application No. 2007-0090406, dated Jun. 22, 2009, along with an English translation.

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