Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-05-05
2011-11-01
Patel, Kaushikkumar (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S130000
Reexamination Certificate
active
08051248
ABSTRACT:
In one embodiment, a processor comprises an execution core, a level 1 (L1) data cache coupled to the execution core and configured to store data, and a transient/transactional cache (TTC) coupled to the execution core. The execution core is configured to generate memory read and write operations responsive to instruction execution, and to generate transactional read and write operations responsive to executing transactional instructions. The L1 data cache is configured to cache memory data accessed responsive to memory read and write operations to identify potentially transient data and to prevent the identified transient data from being stored in the L1 data cache. The TTC is also configured to cache transaction data accessed responsive to transactional read and write operations to track transactions. Each entry in the TTC is usable for transaction data and for transient data.
REFERENCES:
patent: 5428761 (1995-06-01), Herlihy et al.
patent: 6542966 (2003-04-01), Crawford et al.
patent: 6598124 (2003-07-01), Damron et al.
patent: 2005/0108478 (2005-05-01), Holloway et al.
patent: 2008/0126883 (2008-05-01), Caprioli et al.
patent: 2008/0301378 (2008-12-01), Carrie
Bahar et al. (Power and Performance Tradeoffs using Various Caching Strategies), published by ACM, Aug. 10-12, 1998, pp. 64-69.
Hammond et al. (Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software), published 2004 by IEEE computer society, 0272-1732/04, pp. 92-103.
Stephen M. Blackburn, et al., “Transient Caches and Object Streams,” Australian National University Technical Report, TR-CS-06-03, Oct. 2006, 10 pages.
Maurice Herlihy, et al., “Transactional Memory: Architectural Support for Lock-Free Data Structures,” Proceedings of the 20th Annual International Symposium of Computer Architecutre, May 16-19, 1993.
Stephen M. Blackburn, et al. “The Transient Cache: Modern Programs and Modern Cache Design,” 7th Annual Austin CAS International Conference, Feb. 16-17, 2005.
Frank Michael
Haertel Michael J.
Leibs David J.
GLOBALFOUNDRIES Inc.
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Patel Kaushikkumar
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