Transfer gate having overvoltage protection and method

Details Transfer gate having overvoltage protection and method Transfer gate having overvoltage protection and method

2007-10-02

2007-10-02

Tran, Minh-Loan (Department: 2826)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S113000, C361S091100

Reexamination Certificate

active

11280103

ABSTRACT:
A circuit includes a first native or depletion n-channel Metal Oxide Semiconductor (MOS) transistor and a second native or depletion n-channel MOS transistor. The first and second native or depletion n-channel MOS transistors are capable of receiving an input signal. The circuit also includes a standard p-channel MOS transistor and a standard n-channel MOS transistor. The standard MOS transistors are coupled to the native or depletion n-channel MOS transistors and are capable of providing an output signal. The output signal is based on the input signal. Gates of the native or depletion n-channel MOS transistors may be thicker than gates of the standard MOS transistors. The native or depletion n-channel MOS transistors may be capable of blocking excessive voltage from the standard MOS transistors. The standard MOS transistors may be capable of selectively blocking the input signal from the output signal.

REFERENCES:
patent: 6384631 (2002-05-01), Wert et al.
patent: 6501318 (2002-12-01), Randazzo et al.
patent: 6700407 (2004-03-01), Wert

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