Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
1997-12-10
2001-04-17
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S261000, C710S262000, C710S264000, C710S265000
Reexamination Certificate
active
06219741
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a processor system and, more particularly, to a processor system including processors that provide task priority update transactions and end-of-interrupt transactions on a processor bus.
2. Background Art
Processors such as the Pentium® processor and the Pentium® Pro processor manufactured by Intel Corporation are often used in multi-processor systems. Various devices including input and/or output (I/O) devices and other processors may seek to interrupt a processor. To interrupt a processor, an I/O device provides a signal to an interrupt controller, which in turn presents an interrupt request to the processor.
In the case of the Pentium® processor and Pentium® Pro processor, the interrupt controller communicates interrupt information to the processors through a three-wire serial bus, called an APIC (Advanced Programmable Interrupt Controller) bus. The APIC serial bus includes two data conductors and a clock signal conductor.
The Pentium® processor and Pentium® Pro processor include an internal APIC. The APIC includes a local mask register called a Task Priority Register (TPR) that has 8 bits to designate up to 256 priority states, although some of them are reserved. The contents of the TPR is changed to reflect the level of priority of the tasks being performed by the processor.
A lowest priority interrupt is one that although directed to a particular processor, may be redirected to a processor in a group of processors having the lowest priority in its TPR. The arbitration process involves comparing the 8 bits of the TPR of each processor participating in the arbitration. The bits of each processor are asserted one bit at a time, beginning with the most significant bit (MSB), onto the APIC bus line, which is connected in an open drain arrangement to each of the processors. The bits are inverted onto the APIC bus line so that a low voltage (0) has a higher priority that a high voltage (1). First, the MSB from the TPR of each processor participating in the arbitration is asserted on the APIC bus line. If any of the processors asserts a low voltage on the APIC bus line, the line is pulled low. A processor asserting a high voltage discovers there is another processor with a lower priority if the APIC bus line is pulled low. The processor drops out of consideration if another processor has a lower priority. Then, the second MSB from the TPR of each remaining processor is asserted on the APIC bus line. If a processor asserts a high voltage as the second MSB, but the line is pulled low, the processor drops out of consideration. The third MSB and later the fourth MSB of each remaining processor are asserted on the APIC bus line in similar fashion and so forth to the least significant bit (LSB). If two or more processors have equal priorities after all eight bits have been asserted, the processor with the lowest local APIC identification (ID) number is chosen to receive the interrupt vector. The local APIC ID number is assigned at power up.
The APIC serial bus is also used to provide end-of-interrupt (EOI) signals to interrupt controllers. In the case of level triggered interrupts, a state bit in an I/O redirection table in the interrupt controller is set when an interrupt request is sent to a processor. The state bit is reset when the EOI signal is received by the interrupt controller. If a level triggered interrupt signal is detected at the interrupt controller input port after the EOI is received, the interrupt controller sends an interrupt signal to the processors in response to that interrupt signal.
There are certain disadvantages with the APIC serial bus. First, the serial bus is poor at voltage scaling between the interrupt controller (e.g., 3.3 volts) and the processor (e.g., 2.5 or 1.8 volts). It is difficult for provide transistors in a processor that interface between such disparate voltages. As the voltage of the processor core decreases with new generations of processors, the problem will be even greater.
Second, the frequency of the processor core (e.g., often much greater than 200 MHz) is much greater than the frequency of the APIC serial bus (e.g., 16 MHz). As processor frequencies increase, the problem will be even greater. It is difficult to interface between such disparate frequencies. The problem is greater because the signals are independent of each other.
Third, the APIC serial bus is relatively slow. In some implementations, it takes roughly 2 to 3 microseconds to deliver an interrupt. As more I/O intensive functions are used, the speed at which the serial bus can deliver interrupts becomes limiting.
The present invention is directed to over coming or reducing the effect of one or more the above-recited problems with the APIC serial bus.
SUMMARY OF THE INVENTION
In one embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus a task priority update transaction including data representative of a task priority designation of a processor of the computer system, and to provide a signal responsive thereto. The apparatus also includes remote priority capture logic to receive the signal responsive to the task priority update transaction and update contents of the remote priority capture logic in response thereto.
In another embodiment, the invention includes an apparatus for use with a computer system having a processor bus. The apparatus includes decode logic to receive through the processor bus an end-of-interrupt (EOI) transactions and to provide an EOI signal responsive thereto. The apparatus also includes an interrupt controller including a table having a state bit that is set in response to the interrupt controller receiving an interrupt signal and reset in response to the interrupt controller receiving the EOI signal.
REFERENCES:
patent: 5283904 (1994-02-01), Carson et al.
patent: 5511200 (1996-04-01), Jayakumar
patent: 5696976 (1997-12-01), Nizar et al.
patent: 5721931 (1998-02-01), Gephardt et al.
patent: 5758169 (1998-05-01), Nixar et al.
patent: 5848279 (1998-12-01), Wu et al.
patent: 5857090 (1999-01-01), Davis et al.
patent: 5881293 (1999-03-01), Olarig et al.
patent: 6041377 (2000-03-01), Mayer et al.
Lau Daniel G.
Pawlowski Stephen S.
Weier Kimberly C.
Aldous Alan K.
Dharia Rupal D.
Intel Corporation
Sheikh Ayaz R.
LandOfFree
Transactions supporting interrupt destination redirection... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transactions supporting interrupt destination redirection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transactions supporting interrupt destination redirection... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2552703