Transactional flow management interrupt debug architecture

Details Transactional flow management interrupt debug architecture Transactional flow management interrupt debug architecture

2006-12-29

2009-11-17

McCarthy, Christopher S (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S025000, C714S030000, C714S043000

Reexamination Certificate

active

07620840

ABSTRACT:
According to some embodiments, a first bus may be monitored, via a first debug gate, the first bus being to exchange data between a first processing system and a second processing system. A second bus may also be monitored, via a second debug gate, the second bus being to exchange data between the second processing system and a third processing system. Responsive to the monitoring of at least one of the first or second buses, execution of applications, executing on at least two of the processing units, may be interrupted.

REFERENCES:
patent: 6289473 (2001-09-01), Takase
patent: 6918058 (2005-07-01), Miura et al.
patent: 7055139 (2006-05-01), Balle et al.
patent: 7124404 (2006-10-01), Bebout et al.
patent: 2005/0210327 (2005-09-01), Allue et al.
patent: 2007/0006042 (2007-01-01), Beukema et al.
patent: 2007/0105607 (2007-05-01), Russell et al.
patent: 2007/0139421 (2007-06-01), Chen et al.

Affiliated with

Also associated with

Rating

Transactional flow management interrupt debug architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transactional flow management interrupt debug architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transactional flow management interrupt debug architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4117141