Transaction scheduling for a bus system

Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture

Reexamination Certificate

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Details

C710S306000, C710S310000, C710S311000, C710S314000, C710S315000, C370S402000, C370S469000

Reexamination Certificate

active

06792495

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of data communication in a digital system. More particularly, the present invention relates to host controllers and hubs used to transfer information on a bus.
BACKGROUND OF THE INVENTION
A computer or similar device typically has a bus that connects devices to the computing system. Due to a variety of advances (e.g., computing power) in computing systems and devices, the amount of data that can be exchanged between a computing system and its attached devices has increased, requiring a concomitant increase in the bandwidth of the bus. Part of this increased demand for bandwidth has come from multi-media applications that require data to be transferred at regular time intervals (isochronous) either from the device to the computing system (in) via the bus, or in the opposite direction (out). Examples of devices requiring significant bandwidth include cameras, compact disc players, speakers, microphones, video display devices, scanners, and joy-sticks and mice, among other devices.
The bandwidth available on a bus architecture is partly determined by three factors: transmission medium, topology, and the protocol used to control access to the medium. The protocol and topology partly determine the nature of the relationship between a device and a computing system. One possible relationship is a master-slave relationship. In a master-slave relationship the computing system initiates typically all data transactions between the computing system and a device; i.e., the device only responds to requests from the computing system but never initiates a transaction. A benefit of the master-slave relationship is a bus architecture having relatively low cost and simplicity. The Universal Serial Bus (USB) Specification Revision 1.1, Sep. 23, 1998, is an example of a popular bus architecture having a master-slave relationship between elements connected by the bus. Unfortunately, many of today's devices and computing systems have bandwidth requirements (or data rates) that cannot be supported by existing master-slave bus standards, such as the USB Standard.
Even though USB does not support relatively high data rates, it has a relatively large base of users, and supports two data rates: 12 Mb/s (“full-speed”) and 1.5 Mb/s (“low-speed”). USB allows multiple data rates on a bus because some devices do not require high data rates and can achieve significant cost savings by taking advantage of relatively low-cost, low data-rate drivers and cabling.
However, the USB protocol that allows the computing system to communicate at low-speed with low data rate devices and alternatively at full-speed with high data rate devices (speed-shifting) results in the amount of data actually transmitted over the bus (effective throughput) being less than that achievable by limiting the bus to full-speed transactions. In other words, speed shifting results in less bandwidth being available for higher speed (e.g., full-speed) devices, especially when there is a relatively large number of low-speed devices attached to the computing system. The effect of speed shifting on throughput is exacerbated where the ratio of high data rate to low data rate is relatively large.
Another possible bus protocol would require the host to (1) transmit at a high data rate a packet to a hub, (2) wait for the hub to forward at the low data rate the packet to the agent, (3) wait for the agent to respond at the low data rate to the hub, and (4) receive from the hub at a high data rate the agent's response to the packet. When the ratio of the high data rate to the low data rate is relatively large, this bus protocol may also result in a low effective throughput or bandwidth because of the need to wait for the hub to forward the packet at the low data rate and for the agent to respond at the low data rate.
Another popular bus technology is defined by “Firewire” or Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 for a High Performance Serial Bus, 1995. IEEE 1394 supports multiple data rates, up to 400 Mb/s. While the aggregate bandwidth is substantially,higher than USB, IEEE 1394 employs wasteful speed shifting and is a relatively costly technology.
The performance of a bus can be significantly affected by speed-shifting, waiting for a hub to perform transactions at a lower data rate than a host data rate, and the ratio of the host's data rate to the agent's data rate. Thus, it is desirable to have a host controller and/or hub-that allow communication at the higher data rates required by today's bandwidth intensive systems while allowing backward compatibility with pre-existing solutions, such as USB, and without having to pay the penalties imposed by speed-shifting and the other disadvantages of the prior art.
One issue faced by high data rate systems communicating with low data rate devices has been described above. Another issue faced by computing systems arises from the multiplicity of bus protocols (or standards) that are available. Typically, a device manufactured to operate in accordance with a bus protocol will not operate in accordance with a different bus protocol. It may be wasteful to require a user to own largely duplicate devices simply because of differences in the protocol. Where there is a large base of devices being used that have a significant economic life, it may be desirable to allow such devices to be used with a computing system that has a host controller and/or an associated hub that provides backward compatibility to the protocol of the legacy devices.
SUMMARY OF THE INVENTION
According to an embodiment of the invention a method for communicating data using a hub is described. The method includes the step of buffering a single transfer request received at a hub during a transaction between the hub and a host controller, where the single transfer request is to be performed between the hub and an agent to generate a result. The method then includes the step of determining whether a transfer inquiry received at the hub from the host controller corresponds to the result.


REFERENCES:
patent: 5553310 (1996-09-01), Taylor et al.
patent: 5708794 (1998-01-01), Parks et al.
patent: 5742847 (1998-04-01), Knoll et al.
patent: 5870567 (1999-02-01), Hausauer et al.
patent: 5881255 (1999-03-01), Kondo et al.
patent: 5933611 (1999-08-01), Shakkarwar
patent: 6145039 (2000-11-01), Ajanovic et al.
patent: 6243778 (2001-06-01), Fung et al.
patent: 6366590 (2002-04-01), Hu
patent: 6389029 (2002-05-01), McAlear
Patent Abstracts of Japan, vol. 1997, No. 06, Jun. 30, 1997 & JP 09 044443 A (NEC Eng Ltd), Feb. 14, 1997.

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