Transaction retry in multi-processor system

Details Transaction retry in multi-processor system Transaction retry in multi-processor system

2000-09-25

2004-02-10

Auve, Glenn A. (Department: 2189)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S032000, C710S036000, C710S059000

Reexamination Certificate

active

06691191

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to information-processing devices, information-processing methods, and processors, and particularly relates to an information-processing device, an information-processing method, and a processor which perform a transaction-retry operation.
2. Description of the Related Art
As large-scale servers are more widely used, there are expectations that multi-processor systems having a high data-processing capacity and a sufficient reliability will soon be available.
One of the most important factors that control performance of multi-processor systems is speed of a system bus. In order to increase speed of a system bus, the system bus may be pipelined.
A pipelined system bus can increase throughput of the bus. When error occurs, however, a flow of the pipeline operation is disturbed, resulting in a drop in performance. There are various schemes that are developed to avoid the performance drop at the time of error.
One of such schemes is a retry operation. The retry operation resumes a failed process by reissuing an address transaction that caused an error. Since the retry operation is a very important factor that controls performance of a multi-processor system, a reliable and high performance retry operation is necessary.
A pipelined system bus is configured such that an address transaction is divided into a plurality of stages, and that buses corresponding to the respective stages can process transactions independently of each other. Namely, pipelined transactions are performed.
Among various multi-processor systems, multi-processor systems of a shared memory type are regarded as that of a mainstream. The multi-processor systems of a shared memory type have a plurality of processors accessing a shared memory, so that address snooping is performed across the entire system, thereby maintaining coherency.
In such systems, two types of errors are observed. One is an error caused by a system failure or the like, and the other is an error that frequently occurs during a routine or normal operation because of address conflict or the like.
The address conflict occurs when two transactions accessing the same address are successively issued, and results of the first transaction are not available when the second transaction needs to refer them.
There are two methods to cope with this situation. The first method is to suspend the bus until the second transaction can be performed. The second method is to terminate the second transaction and to issue the same address to the bus.
The second method is called an address retry method, and a mechanism for performing an address retry operation is called an address-retry mechanism. Most of the related-art multi-processor systems are provided with an address-retry mechanism in order to prevent a decrease in system performance.
FIG. 1
is a block diagram of a related-art multi-processor system.
A multi-processor system
1
includes processors
2
-
1
through
2
-N, a shared memory
3
, an input-output device
4
, a bus-control unit
5
, and a system bus
6
.
The processors
2
-
1
through
2
-N perform operations according to instructions.
The memory
3
is connected to the N processors
2
-
1
through
2
-N via the system bus
6
, and is accessible from the N processors
2
-
1
through
2
-N. The memory
3
is shared by the processors
2
-
1
through
2
-N.
The input-output device
4
is comprised of a keyboard, a mouse, a display, a printer, a communication device, and the like. The input-output device
4
attends to data inputting/outputting, instruction inputting, processing result inputting/outputting.
The bus-control unit
5
is connected to the N processors
2
-
1
through
2
-N and the input-output device
4
, and controls the right to use the bus
6
. The bus
6
is used for data transfer between the N processors
2
-
1
through
2
-N, the memory
3
, and the input-output device
4
.
FIG. 2
is a block diagram showing a configuration of a processor shown in FIG.
1
.
A processor
2
-X is one of the N processors
2
-
1
through
2
-N. The processor
2
-X and the bus-control unit
5
are connected via the bus
6
. The bus
6
includes an address bus
11
, an address bus
12
, a status bus
13
, a status bus
14
, and a data bus
15
.
The address bus
11
transfers addresses from the processor
2
-X to the bus-control unit
5
. Addresses transferred through the address bus
11
are issued by the processor
2
-X for transaction purposes, for example.
The address bus
12
transfers addresses from the bus-control unit
5
to the processor
2
-X. Addresses transferred through the address bus
12
are arbitrated by the bus-control unit
5
so that permission to use the bus
6
is granted to these addresses, for example.
The status bus
13
delivers statuses of the processor
2
-X from the processor
2
-X to the bus-control unit
5
. The statuses delivered by the status bus
13
include results of cache snooping performed by the processor
2
-X.
The status bus
14
supplies statuses from the bus-control unit
5
to the processor
2
-X. The statuses carried through the status bus
14
include combined results of cache snooping for the N processors
2
-
1
through
2
-N. The data bus
15
transfers data according to the results of the cache snooping.
In the following, a related-art address-transaction process will be described.
The processor
2
-X includes an arithmetic-logic unit
21
, an address-control unit
22
, and a snooping-control unit
23
.
The arithmetic-logic unit
21
attends to data processing, and requests an address transaction according to the results of the data processing. The address-control unit
22
issues an address in response to the address-transaction request made by the arithmetic-logic unit
21
.
The address-control unit
22
includes a queue-issuing unit
22
a
, a retry-control unit
22
b
, and a counter unit
22
c
. The queue-issuing unit
22
a
issues an address in accordance with the address transaction.
The retry-control unit
22
b
is connected to the arithmetic-logic unit
21
, the snooping-control unit
23
, and the bus-control unit
5
. The retry-control unit
22
b
controls the queue-issuing unit
22
a
according to retry instruction sent from the snooping-control unit
23
.
When this happens, the retry-control unit
22
b
has a retry count and/or a time limit recorded therein as they are sent from the arithmetic-logic unit
21
. The counter unit
22
c
supplies a retry count and/or a time that are counted therein to the retry-control unit
22
b
. The retry-control unit
22
b
repeats a retry operation until the retry count or the time supplied from the counter unit
22
c
becomes the retry count or the time limit stored therein.
The retry-control unit
22
b
further stores therein a status of use of the bus
6
that is reported from the bus-control unit
5
. The retry-control unit
22
b
controls frequency of retry operations according to the status reported by the bus-control unit
5
.
The counter unit
22
c
counts a retry count, and/or marks time. The retry-control unit
22
b
refers to the retry count and/or the marked time supplied from the counter unit
22
c
, and limits the retry operations to a predetermined number or to be within the predetermined time period.
The snooping-control unit
23
obtains a cache status from the bus-control unit
5
in response to an address. The snooping-control unit
23
controls data transfer in response to the cache statuses of the entire system that are reported from the bus-control unit
5
, and issues an instruction for an address retry.
In what follows, operation at the time of address transaction will be described.
At a first step, the arithmetic-logic unit
21
of the processor
2
-X issues an address-transaction request. The address transaction request issued by the arithmetic-logic unit
21
is supplied to the queue-issuing unit
22
a
of the address-control unit
22
.
At a second step, the queue-issuing unit
22
a
issues an address in response to the address transaction request

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