Transaction request servicing mechanism

Details Transaction request servicing mechanism Transaction request servicing mechanism

2007-02-20

2007-02-20

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S311000, C710S317000, C710S306000, C710S020000, C711S119000, C711S158000, C370S389000, C709S230000

Reexamination Certificate

active

10743537

ABSTRACT:
A data processing apparatus comprises a master device150, 160, 170, 180, a slave device110, 120, 130and a communication bus140via which transaction requests are passed from master to slave. A transaction annotator of the master device generates transaction identifiers having a master identifier portion and a priority request portion. The slave device determines an order of servicing of transaction requests in dependence upon transaction ordering requests at least partially derived from the master identifier portions and in dependence upon priority values specified in the priority request portions.

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