Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-07-28
2009-02-03
Auve, Glenn A (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S313000, C710S316000, C370S351000
Reexamination Certificate
active
07487284
ABSTRACT:
An apparatus and method for controlling data traffic flow and data ordering of packet data between one or more peripheral devices and a processor/memory combination by using a packet processing engine, located within an input-output hub (IOH). The IOH may include a packet processing engine, and a switch to route packet data between the one or more peripheral devices and the packet processing engine. The packet processing engine of the IOH may control data traffic flow and data ordering of the packet data to and from the one or more peripheral devices through the switch and also maintains flow and ordering to the processor/memory subsystem. The packet processing engine may be operable to perform packet processing operations, such as virtualization of a peripheral device or Transmission Control Protocol/Internet Protocol (TCP/IP) offload.
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Kapur Suvansh Krishan
Nayyar Raman
Oztaskin Ali S.
Auve Glenn A
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
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