Transaction credit control for serial I/O systems

Details Transaction credit control for serial I/O systems Transaction credit control for serial I/O systems

2002-07-29

2004-07-06

Fleming, Fritz (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S029000

Reexamination Certificate

active

06760793

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to information processing systems and more particular to a methodology and implemention for buffer management and transaction control for serialized input/output transactions.
BACKGROUND OF THE INVENTION
In computer systems today, the predominate input/output (I/O) subsystem in Notebooks, desktops, and servers is based on either the so-called PCI (peripheral component interconnect) or PCIX bus (see the Revision 2.3 PCI Local Bus Specification dated Mar. 29, 2002, and the Revision 1.0a PCIX Addendum to the PCI Local Bus Specification dated Jul. 24, 2000). However, in order to keep pace with the growing need to provide improved performance and scalability needs of the future, the PCI-SIG (Peripheral Component Interconnect Special Interest Group) is adopting a new PCI interconnect called “PCI Express”, herein after referred to as “Express”. Express is also referred to as “3GIO” in some versions of the Express specification. Express is a serial point-to-point switched fabric interconnect that utilizes the same programming model as the current PCI and PCIX bus definitions. PCI and PCIX provide a set of transaction ordering rules that define the requirements as to whether a second transaction of various transaction types must be allowed or not allowed to bypass a first transaction of various transaction types. These transaction ordering rules result in significant complexity in PCI and PCIX devices, especially for PCIX—PCIX (and PCI—PCI) bridges. Express also introduces the concept of multi-port switches. The Express specification defines an Express switch as a logical assembly of multiple virtual PCI—PCI bridge devices that have one primary interface and multiple secondary interfaces, with each external interface being an Express serial interface. An Express switch by definition is even more complex than today's typical PCIX—PCIX bridge (which are themselves very complex devices). Express carries over the transaction ordering rules of PCI essentially unchanged, such that when adding the serial nature and other features of Express, this results in very significant complexity for Express devices and introduces other problems.
Thus, there is a need for an improved method, circuit, and system for Express switches, Express-PCI bridges and other Express devices to improve transaction ordering and buffer management requirements for data consistency, and also to avoid data transfer congestion and deadlocks.
SUMMARY OF THE INVENTION
A method and implementing computer system are provided which allow for much improved input/output (I/O) subsystem designs for use in serialized I/O transaction systems including Express systems. To achieve improved scalability, Express adds to PCI/PCIX a serial point-to-point signaling capability at the Express link and chip interface. This invention defines means to greatly improve Express design requirements, making the design of Express devices such as an Express switch, Express-PCI bridge, endpoint, or root complex more efficient, less complex and therefore less costly. This is accomplished by improving the requirements for input buffer designs and transaction credit types and credit control for managing the flow of transactions across a serial I/O link. An improved transaction credit and flow control is provided which results in significant performance improvements as transactions flow through Express devices and over Express links.


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