Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2011-07-19
2011-07-19
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S150000, C711S205000, C711SE12022, C711SE12032
Reexamination Certificate
active
07984248
ABSTRACT:
The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.
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Crawford John H.
Kottapalli Sailesh
Vaid Kushagra
Bragdon Reginald G
Intel Corporation
McAbee David P.
Ruiz Aracelis
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