Traffic controller using priority and burst control for...

Details Traffic controller using priority and burst control for... Traffic controller using priority and burst control for...

2005-08-23

2005-08-23

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C710S057000, C711S105000, C711S106000, C711S157000, C365S222000

Reexamination Certificate

active

06934820

ABSTRACT:
A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

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