Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-05-16
2006-05-16
Beausoliel, Robert (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C710S068000
Reexamination Certificate
active
07047451
ABSTRACT:
A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.
REFERENCES:
patent: 6813731 (2004-11-01), Zahavi et al.
patent: 6839869 (2005-01-01), Doi et al.
patent: 6918065 (2005-07-01), Edwards et al.
patent: 2002/0055830 (2002-05-01), Swoboda et al.
patent: 2005/0138483 (2005-06-01), Hatonen et al.
Agarwala Manisha
Gill Maria B. H.
Johnsen John M.
Nardini Lewis
Swoboda Gary L.
Beausoliel Robert
Brady III W. James
Duncan Marc
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
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