Trace fifo management

Details Trace fifo management Trace fifo management

1999-10-01

2003-01-14

Beausoleil, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

06507921

ABSTRACT:

This application claims priority to S.N. 99400559.3, filed in Europe on Mar. 8, 1999 (TI-27759EU) and S.N. 98402455.4, filed in Europe on Oct. 6, 1998 (TI-28433EU).
FIELD OF THE INVENTION
The present invention relates to digital microprocessors, and more particularly to monitoring the operation of digital microprocessors.
BACKGROUND OF THE INVENTION
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A software developer may want to trace the execution sequence of a program in order to determine actual execution sequence and then modify the program in order to optimize execution performance. Similarly, a software developer may want to trace the execution sequence of a program in order to identify an error. However, tracing a processor with limited external buses or on board caches is difficult or impossible.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as mobile telecommunications applications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a microprocessor that is a programmable digital signal processor (DSP), offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The microprocessor has an instruction buffer unit operable to decode a first instruction of the sequence of instructions and a means for providing an instruction address that identifies the first instruction in the sequence of instructions to be decoded by the instruction buffer unit. Furthermore, the microprocessor has a means for tracing the instruction address of the first instruction that is operable to store the address of the first instruction only if the first instruction is adjacent to a discontinuity in the sequence of instructions.
In accordance with another aspect of the present invention, the means for tracing is further operable to store a first length format data item indicative of a length of the first instruction.
In accordance with another aspect of the present invention, the means for tracing is further operable to store a first repeat instruction format data item if the first instruction is a repeat instruction, such that an address of the first instruction is stored only once by the means for tracing if the first instruction is a repeat instruction.
In accordance with another aspect of the present invention, a method of operating a digital system is provided. A microprocessor is operable to trace a sequence of instruction addresses by providing an instruction address that identifies a first instruction in a sequence of instructions to be decoded by an instruction buffer unit, decoding the first instruction of the sequence of instructions in the instruction buffer unit, and then tracing the instruction address of the first instruction by storing the address of the first instruction only if the first instruction is adjacent to a discontinuity in the sequence of instruction addresses. These steps are repeated to form a sequence of discontinuity addresses. The sequence of instruction addresses is reconstructed by interpolating between each discontinuity in the sequence of discontinuity addresses.


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