Trace circuit

Details Trace circuit Trace circuit

2001-08-03

2004-11-02

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C703S028000

Reexamination Certificate

active

06813732

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a trace circuit built into a debugging circuit which is, in turn, built into a microcomputer of a device.
BACKGROUND OF THE INVENTION
Conventionally, it is common to use an in-circuit emulator (ICE) for debugging programs of a microcomputer. The ICE emulates a function of a microcomputer for program debugging. Address bus, data bus and control bus of the microcomputer are connected to the memory of the ICE. A program is downloaded, in the memory of the ICE, from the host computer that controls the ICE. The ICE, based on the downloaded program, operates the microcomputer.
The microcomputer of the ICE is replaced by a microcomputer which is the object of program debugging. Thereafter the program debugging is performed.
In a general microcomputer-embedded-typed LSI, the address bus and data bus and so on for connecting to the memory of the ICE are not connected to the LSI terminal. This is because the program is stored in a memory embedded in the microcomputer. Therefore, a mode only used for ICE connection is prepared. An address bus and a data bus are extended from the external terminal of the LSI. In addition, the original function, with the terminal used as an address bus and a data bus, is carried out within the ICE.
However, because several terminals of the microcomputer need to be connected between the ICE and the target system, the connection between ICE and the target system has become difficult, accompanying an improvement in speed of a microcomputer or a multi-bit bus. Furthermore, the various functions for system realization, other than a microcomputer, are embedded in LSI in system LSI in which a microcomputer is embedded, so that it has become difficult to emulate the original function which the terminal used as an address bus or a data bus for connection with the memory of ICE has, using the ICE.
The debugging circuit performing the function, which the ICE conventionally has on the basis of the foregoing description, is embedded in a microcomputer, and a program development technique has been adopted such that the emulator (debugger) is connected to a host computer through an LSI terminal only for debugging.
FIG. 6
shows an internal circuit arrangement of the conventional microcomputer-embedded LSI
1
. Reference numeral
2
denotes a bus interface. Reference numeral
3
denotes a CPU. Reference numeral
4
denotes a memory. Reference numeral
5
denotes a debugging circuit Reference numeral
6
denotes a trace circuit in the debugging circuit. Reference numeral
7
denotes a control circuit (event control circuit). Reference numeral
8
denotes a trace buffer memory. Reference numeral
9
denotes an output latching circuit. Reference numeral
10
denotes an output control circuit Reference numeral
11
denotes a control bus. Reference numeral
12
denotes an address bus. Reference numeral
13
denotes a data bus. Reference numeral
14
denotes a control bus. Reference numeral
15
denotes an address bus. Reference numeral
16
denotes a data bus. Reference numerals
14
,
15
and
16
denote trace buses. Data is output from the trace circuit
6
through the LSI data output terminal DATA. This data is constituted by 4 bits.
FIG. 7
shows a timing chart of various signals in this trace circuit
6
. Any desired data (8 bits) of the control bus
14
, the address bus
15
, and the data bus
16
is stored in the trace buffer memory
8
through the event control circuit
7
based on a signal WRITE that is synchronized with the bus clock signal CK. The data once D stored in the trace buffer memory
8
is output, based on subsequent READ signals, from the trace buffer memory
8
to the output latch circuit
9
and is further input into the output control circuit
10
. The output control circuit
10
converts 8-bit data to 4-bit data, which is output through the terminal DATA, using the output control signals S
1
and S
2
, each of whose frequency is the same as the bus clock signal CK frequency and whose phase is shifted by only &pgr; through the terminal DATA. In
FIG. 7
, ABh, CDh, 12h, 34h are hexadecimal numbers. Furthermore, in FIG.
6
and
FIG. 7
, A
1
, A
2
, A
3
, and A
4
are 8-bit data stored in sequence in the trace buffer memory
8
.
However, the processing speed of the microcomputer in the system LSI in recent years is becoming faster and the bus clock frequency therein is increasing. As a result, in the conventional case, access speed to a trace buffer memory cannot catch up with the speed at which data is transmitted from the control circuit. In other words, since one bus cycle is becoming shorter and shorter, it is becoming difficult to store the input data in the trace buffer memory or to output the data from it during one bus cycle.
SUMMARY OF THE INVENTION
It is an object of the present invention to obtain a trace circuit capable of surely transferring data to an emulator through a trace buffer memory, even if a bus clock frequency is accelerated.
The trace circuit according to the present invention comprises plural trace buffer memories in which the data on the bus of the microcomputer is stored according to the bus clock signal; a control circuit which makes the trace buffer memories store cyclically and in a predetermined order the data on the bus, makes the trace buffer memories output cyclically and in a predetermined order the stored data, wherein the storage of data in and output of data from the trace buffer memories is performed in synchronization with the bus clock signal; and an output terminal through which the data stored in the trace buffer memories is output to the emulator.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.


REFERENCES:
patent: 6055651 (2000-04-01), Sasaki et al.
patent: 6233673 (2001-05-01), Higashida
patent: 6243834 (2001-06-01), Garrett
patent: 6393587 (2002-05-01), Bucher et al.
patent: 2002/0010882 (2002-01-01), Yamashita
patent: 2002/0120815 (2002-08-01), Zahavi et al.
patent: 06052013 (1994-02-01), None
patent: 7-121402 (1995-05-01), None
patent: 9-261226 (1997-10-01), None

Affiliated with

Also associated with

Rating

Trace circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Trace circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Trace circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3275413