Trace buffer for DDR memories

Details Trace buffer for DDR memories Trace buffer for DDR memories

2007-02-13

2007-02-13

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S149000, C711S131000

Reexamination Certificate

active

10803377

ABSTRACT:
A system for storing and retrieving data provided by the system on a system bus in a sequence at a predetermined system data rate. The system includes a system memory controller for enabling a system memory to store and retrieve the data at a rate twice the system data rate. Also provided is a trace buffer having a dual port random access memory. A trace buffer control system is provided for enabling the data on the system bus and fed concurrently to a pair of data ports of the dual port random access memory to be stored in the dual port random access memory at the predetermined system data rate and for enabling such dual port random access memory stored data to be retrieved from the dual port random access memory in the same sequence as such data was provided on the system data bus.

REFERENCES:
patent: 6216205 (2001-04-01), Chin et al.
patent: 2003/0023823 (2003-01-01), Woo et al.
patent: 2004/0068614 (2004-04-01), Rosenbluth et al.

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