Trace based instruction caching

Details Trace based instruction caching Trace based instruction caching

1997-10-23

2000-01-25

Lane, Jack A.

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Dynamic-type storage device

711125, 712230, G06F 926, G06F 1200

Patent

active

060187867

ABSTRACT:
A cache memory is constituted with a data array and control logic. The data array includes a number of data lines, and the control logic operates to store a number of trace segments of instructions in the data lines, including trace segments that span multiple data lines. In one embodiment, each trace segment includes one or more trace segment members having one or more instructions, with each trace segment member occupying one data line, and the data lines of a multi-line trace segment being sequentially associated (logically). Retrieval of the trace segment members of a multi-line trace segment is accomplished by first locating the data line storing the first trace segment member of the trace segment, and then successively locating the remaining data lines storing the remaining trace segment members based on the data lines' logical sequential associations.

REFERENCES:
patent: 5381533 (1995-01-01), Peleg et al.
Eric Rotenberg, Steve Bennett & Jim Smith, "Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching," dated Apr. 11, 1996, 48 pages.
Stephen W. Melvin, Michael C. Shebanow & Yale N. Patt, "Hardware Support for Large Atomic Units in Dynamically Scheduled Machines," Computer Science Division, University of California Berkeley, 1988 IEEE, pp. 60-63.
PCT International Search Report, International Application No. PCT/US99/00959, Jan. 15, 1999, 5 pages.

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