Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2005-03-17
2008-01-29
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257SE29119, C257SE23011, C257SE21577, C257SE23145, C438S637000, C438S672000
Reexamination Certificate
active
07323784
ABSTRACT:
Top via pattern for a bond pad structure has at least one first via group and at least one second via group adjacent to each other. The first via group has at least two line vias extending in a first direction. The second via group has at least two line vias extending in a second direction different from said first direction. The line via of the first via group does not cross the line via of the second via group.
REFERENCES:
patent: 6163074 (2000-12-01), Lee et al.
patent: 6306750 (2001-10-01), Huang et al.
patent: 6552435 (2003-04-01), Noble
patent: 6822329 (2004-11-01), Varrot et al.
patent: 2001/0009802 (2001-07-01), Lee
patent: 2004/0021227 (2004-02-01), Watanabe
patent: 2001-261199 (2001-09-01), None
patent: 2002-134509 (2002-05-01), None
Chen Ming-Hsien
Fan Fu-Jier
Lin Huang-Sheng
Shiue Ruey-Yun
Wang Aaron
Coleman W. David
Kim Su C.
Taiwan Semiconductor Manufacturing Co. Ltd.
LandOfFree
Top via pattern for bond pad structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Top via pattern for bond pad structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Top via pattern for bond pad structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3963396