Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2004-07-21
2009-10-13
Gurley, Lynne A. (Department: 2811)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C257SE21245
Reexamination Certificate
active
07601646
ABSTRACT:
Manufacturing yield of integrated circuits having differentiated areas such as array and support areas of a memory is improved by reducing height/step height difference between structures in the respective differentiated areas and is particularly effective in conjunction with top-oxide-early (TOE) and top-oxide-late processes. A novel planarization technique avoids damage of active devices, isolation structures and the like due to scratching, chipping or dishing which is particularly effective to improve manufacturing yield using TON processes and also using TOE and TOL processes when average height/step height is substantially equalized. Alternative mask materials such as polysilicon may also be used to simplify and/or improve control of processes.
REFERENCES:
patent: 5780339 (1998-07-01), Liu et al.
patent: 5883006 (1999-03-01), Iba
patent: 5895946 (1999-04-01), Hamamoto et al.
patent: 6100138 (2000-08-01), Tu
patent: 6103623 (2000-08-01), Lien et al.
patent: 6124165 (2000-09-01), Lien
patent: 6165839 (2000-12-01), Lee et al.
patent: 6403494 (2002-06-01), Chu et al.
patent: 6429068 (2002-08-01), Divakaruni et al.
patent: 6509226 (2003-01-01), Jaiprakash et al.
patent: 6576526 (2003-06-01), Kai et al.
patent: 6617213 (2003-09-01), Hummler
patent: 6617245 (2003-09-01), Ueda
patent: 6620677 (2003-09-01), Hummler
patent: 6673686 (2004-01-01), Scholz et al.
patent: 6709924 (2004-03-01), Yu et al.
patent: 6716764 (2004-04-01), Girard et al.
patent: 6730980 (2004-05-01), Rhodes
patent: 6837965 (2005-01-01), Gustafson et al.
patent: 2003/0143809 (2003-07-01), Hummler
patent: 2003/0186502 (2003-10-01), Malik et al.
patent: 2004/0033659 (2004-02-01), Seitz et al.
patent: 2004/0075111 (2004-04-01), Chidambarrao et al.
Akatsu Hiroyuki
Divakaruni Ramachandra
Kim Byeong
Kim Deok-kee
Strane Jay
Arena Andrew O.
Gurley Lynne A.
International Business Machines - Corporation
Whitham Curtis Christofferson & Cook, P.C.
LandOfFree
Top-oxide-early process and array top oxide planarization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Top-oxide-early process and array top oxide planarization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Top-oxide-early process and array top oxide planarization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4117347