Top layers of metal for integrated circuits

Details Top layers of metal for integrated circuits Top layers of metal for integrated circuits

2004-09-23

2008-08-26

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S587000, C438S629000

Reexamination Certificate

active

07416971

ABSTRACT:
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads.

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Co-pending U.S. Patent App. MSL-98-002CCC-CIP, to the same assignee, U.S. Appl. No. 10/154,662, filed May 24, 2002, “Top Layers of Metal for High Performance IC's,”.
Stanley Wolf inSilicon Processing for the VLSI Era, vol. 2, pp. 214-217, Lattice Press, Sunset Beach, CA c.1990.

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