Top layers of metal for high performance IC's

Details Top layers of metal for high performance IC's Top layers of metal for high performance IC's

2008-05-06

2008-05-06

Tsai, H. Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C428S622000, C428S687000, C257SE23161

Reexamination Certificate

active

11230102

ABSTRACT:
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

REFERENCES:
patent: 4423547 (1984-01-01), Farrar et al.
patent: 4618878 (1986-10-01), Aoyama et al.
patent: 5055907 (1991-10-01), Jacobs
patent: 5083187 (1992-01-01), Lamson et al.
patent: 5106461 (1992-04-01), Volfson et al.
patent: 5212403 (1993-05-01), Nakanishi et al.
patent: 5384488 (1995-01-01), Golshan et al.
patent: 5468984 (1995-11-01), Efland et al.
patent: 5501006 (1996-03-01), Gehman, Jr. et al.
patent: 5635767 (1997-06-01), Wenzel et al.
patent: 5659201 (1997-08-01), Wollesen
patent: 5686764 (1997-11-01), Fulcher
patent: 5818110 (1998-10-01), Cronin
patent: 5827776 (1998-10-01), Bandyopadhyay et al.
patent: 5827778 (1998-10-01), Yamada
patent: 5834844 (1998-11-01), Akagawa et al.
patent: 5910020 (1999-06-01), Yamada
patent: 5953626 (1999-09-01), Hause et al.
patent: 5969424 (1999-10-01), Matsuki et al.
patent: 6020640 (2000-02-01), Efland et al.
patent: 6100548 (2000-08-01), Nguyen et al.
patent: 6130457 (2000-10-01), Yu et al.
patent: 6144100 (2000-11-01), Shen et al.
patent: 6184143 (2001-02-01), Ohashi et al.
patent: 6229221 (2001-05-01), Kloen et al.
patent: 6303423 (2001-10-01), Lin
patent: 6383916 (2002-05-01), Lin
patent: 6472745 (2002-10-01), Iizuka
patent: 6707159 (2004-03-01), Kumamoto et al.
patent: 01-135043 (1989-05-01), None
patent: 01-183836 (1989-07-01), None
patent: 01-184848 (1989-07-01), None
patent: 01-184849 (1989-07-01), None
patent: 04-316351 (1992-11-01), None
Stanley Wolf, Ph.D.,Silicon Processing for the VLSI Era =vol. 2 Process Integration, Lattice Press, Sunset Beach, CA, USA Copyright 1990, pp. 214-217, 282-285.

Affiliated with

Also associated with

Rating

Top layers of metal for high performance IC's does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Top layers of metal for high performance IC's, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Top layers of metal for high performance IC's will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3927738