Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Optimization
Reexamination Certificate
2011-08-30
2011-08-30
Levin, Naum (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Optimization
C716S132000, C716S134000, C716S135000, C703S014000
Reexamination Certificate
active
08010931
ABSTRACT:
A configurable logic tool that allows minimization of dynamic power within an FPGA design without changing user-entered specifications. The minimization of power may use minimized clock nets as a first order operation, and a second order operation that minimizes other factors, such as area of placement, area of clocks and/or slack.
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Agarwal Deepak
Davoodi Azadeh
French Matthew C.
Wang Li
Fish & Richardson P.C.
Levin Naum
University of Southern California
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