Tolerant buffer circuit and interface

Details Tolerant buffer circuit and interface Tolerant buffer circuit and interface

2011-03-15

2011-03-15

Barnie, Rexford N (Department: 2819)

Electronic digital logic circuitry

Tri-state

With field-effect transistor

C326S059000, C326S086000, C326S087000

Reexamination Certificate

active

07906988

ABSTRACT:
The tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur, even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. A tolerant buffer circuit is provided with first and second PMOS transistors that are connected in series and that share a source between a power supply terminal and an output terminal, an NMOS transistor connected between the output terminal and a ground terminal, a first inverter output-connected to the gate of the first PMOS transistor, a second inverter output-connected to the gate of the second PMOS transistor, and a control circuit that outputs first, second, and third control signals to the first PMOS transistor, the second PMOS transistor, and the NMOS transistor, respectively, and controls the on/off state of these MOS transistors.

REFERENCES:
patent: 6046626 (2000-04-01), Saeki et al.
patent: 6118301 (2000-09-01), Singh et al.
patent: 6304112 (2001-10-01), Annema et al.
patent: 7375555 (2008-05-01), Wang et al.
patent: 7453310 (2008-11-01), Ota et al.
patent: 2008/0116751 (2008-05-01), Kihara et al.
patent: 5-284001 (1993-10-01), None
patent: 2008-131305 (2008-06-01), None
English language Abstract of JP 5-284001, Oct. 29, 1993.
English language Abstract of JP 2008-131305, Jun. 5, 2008.

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