Tolerance bondwire inductors for analog circuitry

Details Tolerance bondwire inductors for analog circuitry Tolerance bondwire inductors for analog circuitry

2006-11-07

2006-11-07

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S611000, C438S612000, C438S613000, C438S508000, C438S508000

Reexamination Certificate

active

07132359

ABSTRACT:
Disclosed are wirebonding methods wherein bondwires are positioned using dynamically determined variations in die placement. Preferred methods of the invention include steps for placing a die on the prepared substrate using selected ideal placement coordinates. Deviation of the actual die placement from the selected ideal placement coordinates is monitored, and one ore more critical bondwires are wirebonded between respective die pins and pins on the substrate. The monitored placement deviation is used to dynamically position the critical bondwires on the critical pins according to actual die placement. Disclosed embodiments include methods using lateral deviation monitoring and angular deviation monitoring to dynamically position bondwires.

REFERENCES:
patent: 6225143 (2001-05-01), Rao et al.

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