TLB using region ID prevalidation

Details TLB using region ID prevalidation TLB using region ID prevalidation

2000-03-31

2003-05-06

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S152000, C711S108000, C711S220000

Reexamination Certificate

active

06560689

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of computer architecture and more specifically to a translation look-aside buffer for translating virtual addresses to physical addresses.
2. Description of the Related Art
In a computer, a typical practice is to use a translation look-aside buffer (TLB) to translate a virtual address to a physical address. The TLB generally operates to receive all or part of a virtual address and determines if an entry stored in the TLB matches the received virtual address. If there is a match, the TLB provides the physical address stored in the TLB which corresponds to the matched entry. This physical address from the TLB is typically combined with offset bits of the virtual address to generate a complete physical address. In TLB structures, the offset size is a function of the page size for the computer architecture being implemented.
The TLB essentially operates as a fast cache memory, which stores a subset of the total virtual to physical address translation mappings. When a virtual address matches one of the translations stored in the TLB, it is termed a TLB hit. When a TLB hit occurs, the physical address is quickly generated. If there is a miss, a delay is encountered in generating the physical address while the missing address translation is found, placed in the TLB, and a repetition of the original access is performed.
Processor architectures define the virtual addressing scheme to access the physical memory. Although various paging, segmentation, and other schemes can be employed, the addressing scheme is constrained by the number of bits available for processing the addresses. TLBs are designed within these constraints. TLBs using content addressable memory (CAM) can quickly match the virtual address to the entries stored in the TLB. However, as architectures expand from 32 to 64 bits, 128 bits and higher, the achitecture and the addressing scheme become more complex. The complexity often results in slower processor operation.
Accordingly, the present invention pertains to the operation of a TLB in a computer.


REFERENCES:
patent: 5699543 (1997-12-01), Saxena
patent: 5712998 (1998-01-01), Rosen
patent: 5752275 (1998-05-01), Hammond
patent: 5918251 (1999-06-01), Yamada et al.
patent: 5928352 (1999-07-01), Gochman et al.
patent: 5940872 (1999-08-01), Hammond et al.
patent: 6216214 (2001-04-01), Bryg et al.
patent: 6230248 (2001-05-01), Burger et al.
patent: 6408373 (2002-06-01), Burger et al.
patent: 6470437 (2002-10-01), Lyon
Handy, “The Cache Memory Book”, © 1998, Academic Press, Inc., p. 14.

Affiliated with

Also associated with

Rating

TLB using region ID prevalidation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with TLB using region ID prevalidation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and TLB using region ID prevalidation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3051202