TLB miss fault handler and method for accessing multiple...

Details TLB miss fault handler and method for accessing multiple... TLB miss fault handler and method for accessing multiple...

2006-09-19

2006-09-19

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S006000, C711S202000, C711S203000, C711S205000, C711S207000, C717S138000, C703S023000

Reexamination Certificate

active

07111145

ABSTRACT:
A virtual memory system implementing the invention provides concurrent access to translations for virtual addresses from multiple address spaces. One embodiment of the invention is implemented in a virtual computer system, in which a virtual machine monitor supports a virtual machine. In this embodiment, the invention provides concurrent access to translations for virtual addresses from the respective address spaces of both the virtual machine monitor and the virtual machine. Multiple page tables contain the translations for the multiple address spaces. Information about an operating state of the computer system, as well as an address space identifier, are used to determine whether, and under what circumstances, an attempted memory access is permissible. If the attempted memory access is permissible, the address space identifier is also used to determine which of the multiple page tables contains the translation for the attempted memory access.

REFERENCES:
patent: 6606697 (2003-08-01), Kawahara et al.
patent: 6651132 (2003-11-01), Traut
patent: 6725289 (2004-04-01), Waldspurger et al.
patent: 2003/0115578 (2003-06-01), Liokumovich et al.
patent: 2003/0120856 (2003-06-01), Neiger et al.
patent: 2004/0117593 (2004-06-01), Uhlig et al.

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