TLB lock indicator

Details TLB lock indicator TLB lock indicator

2005-08-23

2008-09-16

Elmore, Stephen C (Department: 2185)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S125000, C711S126000, C711S144000, C711S156000, C711S163000

Reexamination Certificate

active

07426626

ABSTRACT:
A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.

REFERENCES:
patent: 4727485 (1988-02-01), Keshlear et al.
patent: 6223263 (2001-04-01), Mathews et al.
patent: 6553477 (2003-04-01), Krishna et al.
patent: 6941442 (2005-09-01), Devereux
patent: 7065625 (2006-06-01), Alderson
patent: 1204029 (2002-05-01), None

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