Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1997-09-23
2000-05-02
Niebling, John F.
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438527, 438528, H01L 2144, H01L 21425
Patent
active
060572205
ABSTRACT:
A "porous barrier" is formed without formation of a discrete barrier layer by enriching grain boundaries of a body of polysilicon with nitrogen to inhibit thermal mobility of silicon species therealong. In a polycide gate/interconnect structure, the reduced mobility of silicon suppresses agglomeration of silicon in a metal silicide layer formed thereon. Since silicon agglomeration is a precursor of a polycide inversion phenomenon, polycide inversion which can pierce an underlying oxide and cause device failure is effectively avoided. The increased thermal stability of polycide structures and other structures including a body of polysilicon thus increases the heat budget that can be withstood by the structure and increases the manufacturing process window imposed by the presence of polysilicon which can be exploited in other processes such as annealing to develop a low resistance phase of refractory metal silicide included in the polycide structure, drive-in annealing for formation of source/drain regions of field effect transistors and the like.
REFERENCES:
patent: 4690730 (1987-09-01), Tang et al.
patent: 4784973 (1988-11-01), Stevens et al.
patent: 4931411 (1990-06-01), Tigelaar et al.
patent: 5330921 (1994-07-01), Yoshida et al.
patent: 5358893 (1994-10-01), Yang et al.
patent: 5518958 (1996-05-01), Giewont et al.
patent: 5536947 (1996-07-01), Klersy et al.
patent: 5543362 (1996-08-01), Wu
patent: 5545574 (1996-08-01), Chen et al.
patent: 5585300 (1996-12-01), Summerfelt
patent: 5739064 (1998-04-01), Hu et al.
patent: 5766991 (1998-06-01), Chen
patent: 5874351 (1999-02-01), Hu et al.
K. Kobushi et al.; "A High Integrity and Low Resistance Ti-Polycide Gate Using a Nitrogen Ion-Implanted Buffer Layer"; Japanese Journal of Applied Physics/Part 2: Letters 27; (1988) Nov.; pp. L2158-L2160.
Hosoya et al.; "A Polycide Gate Electrode with a Conductive Diffusion Barrier Formed with ECR Nitrogen for Dual Gate CMOS"; IEEE Transactions on Electron Devices; vol. 42, No. 12, Dec. 1995; pp. 2111-2116.
P.C. Li and E. Mayen, Gate Dielectric Structure for Field-Effect Transistors, Jan. 1975, IBM Technical Disclosure Bulletin, vol. 17, No. 8, p. 2330.
M.R. Poponiak and P.J. Tsang, Thick Wear Resistant Coatings for Silicon Devices, May 1976, IBM Technical Disclosure Bulletin, vol. 18, No. 12, p. 4008.
Double-Layer Insulation of Polymide and Perforated Nitride, Mar. 1985, IBM Technical Disclosure Bulletin, vol. 27, No. 10A, pp. 5835-5836.
Ajmera Atul C.
Dehm Christine
Domenicucci Anthony G.
Gifford George G.
Loh Stephen K.
Capella, Esq. Steven
Infineon Technologies North America Corporation
International Business Machines - Corporation
Lindsay Jr. Walter L.
Niebling John F.
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