Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2000-08-30
2002-12-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S664000
Reexamination Certificate
active
06495438
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a semiconductor device, and more particularly to a novel titanium polycide gate electrode and a method of forming a titanium polycide gate electrode which has a reduced sheet resistance which is highly stable and also has a high stability in shape.
2. Description of the Related Art
In recent years, in order to reduce the resistance of the gate electrode of the transistor, a double layered gate electrode has been used which has a polysilicon layer and a titanium silicide layer on the polysilicon layer. This gate electrode is so called to as titanium polycide gate electrode.
A conventional method of forming a polycide gate electrode will be described with reference to drawings.
FIGS. 1A through 1D
are fragmentary cross sectional elevation views illustrative of semiconductor devices with polycide gate electrodes in sequential steps involved in a conventional fabrication method for forming the polycide gate electrode.
With reference to
FIG. 1A
, shallow trench isolations
12
are selectively formed in an upper region of a silicon substrate
10
so that the shallow trench isolations
12
define device regions. A gate oxide film
14
is formed on the device regions of the silicon substrate
10
. A polysilicon film
16
is entirely formed on the gate oxide film
14
and also on top portions of the shallow trench isolations
12
.
With reference to
FIG. 1B
, a TiSi
2
film
18
having a compositional ratio of Ti:Si=1:2 is then entirely deposited by a sputtering method on an entire top surface of the polysilicon film
16
. An SiN film
20
is then entirely formed on an entire top surface of the TiSi
2
film
18
.
With reference to
FIG. 1C
, a resist film is entirely applied on the top surface of the SiN film
20
. A lithography process is carried out to pattern the SiN film
20
, whereby an etching mask
22
is selectively formed on a predetermined area of the top surface of the TiSi
2
film
18
.
With reference to
FIG. 1D
, an anisotropic etching is then carried out by use of the etching mask
22
for selectively removing laminations of the TiSi
2
film
18
, the polysilicon film
16
and the gate oxide film
14
except under the etching mask
22
. The used etching mask
22
is then removed. As a result, the gate electrode is formed on the gate oxide film
14
, wherein the gate electrode has a double layered structure which comprises the polysilicon film
16
and the TiSi
2
film
18
.
The above conventional method uses the anisotropic etching process by use of the etching mask
22
for selectively etching the laminations of the TiSi
2
film
18
, the polysilicon film
16
and the gate oxide film
14
except under the etching mask
22
, whereby the top surface of the silicon substrate
10
is shown. The top surface of the silicon substrate
10
receives a damage during the anisotropic etching process for patterning the gate electrode, whereby a surface region of the silicon substrate receives the damage. Namely, a surface damage layer is formed on the surface region of the silicon substrate
10
.
FIG. 2
is a fragmentary cross sectional elevation view illustrative of a semiconductor device with a polycide gate electrode after a rapid thermal oxidation process has been carried out to oxidize a damage layer in accordance with one additional step involved in the conventional fabrication method. In order to attempt to solve the above problem with formation of the damage layer, a rapid thermal oxidation process is carried out for oxidizing the damage layer so that the damage layer becomes an extremely thin silicon dioxide layer
24
. Particularly if silicon nitride side walls are formed on side walls of the gate electrode, then the silicon dioxide film
24
covering the top surface of the silicon substrate
10
improves the resistivity to the hot-carrier.
It had, however, been reported in IEEE 1998, IEDM 98, pp. 389-392, that it is difficult to carry out the rapid thermal oxidation to the substrate with the titanium polycide gate electrode.
The lamp annealer is used to carry out a rapid thermal oxidation at a temperature of 1000° C. for 60 seconds in an oxygen atmosphere in order to oxidize the damage layer on the top surface of the silicon substrate
10
so that the damage layer becomes the extremely thin silicon dioxide film
24
having a thickness of about 50 angstroms. This extremely thin silicon oxide film
24
also serves as a passivation layer for protecting the top surface of the silicon substrate
10
from an ion-implantation to be carried out for forming diffusion layers in upper regions of the silicon substrate
10
.
FIG. 3
is a fragmentary cross sectional elevation view illustrative of a semiconductor device with a titanium polycide gate electrode which has been broken by the rapid thermal oxidation process carried out for oxidizing the damage layer on the top surface of the silicon substrate
10
. Namely, it is possible that the rapid thermal oxidation process for oxidizing the damage layer on the top surface of the silicon substrate
10
causes the lamination structure of the titanium polycide gate electrode to be broken or one layer of the lamination structure to be peeled. As a result, the sheet resistance of the gate electrode is increased and the stability of the sheet resistance of the gate electrode is reduced. This makes it invalid to form the polycide structure gate electrode, if the polycide structure is to reduce the resistance of the gate electrode.
The above problem is common not only to the polycide gate electrode but also to any polycide layers such as a polycide interconnection.
In the above circumstances, it had been required to develop a novel method of forming a polycide gate electrode free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel a titanium polycide layer free from the above problems.
It is another object of the present invention to provide a novel a titanium polycide layer having a reduced sheet resistance which is highly stable.
It is still another object of the present invention to provide a novel a titanium polycide layer having a high stability of lamination structure or shape.
It is yet another object of the present invention to provide a novel titanium polycide gate electrode of a semiconductor device free from the above problems.
It is still more another object of the present invention to provide a novel titanium polycide gate electrode of a semiconductor device having a reduced sheet resistance which is highly stable.
It is yet more another object of the present invention to provide a novel titanium polycide gate electrode of a semiconductor device having a high stability of lamination structure or shape.
It is an additional object of the present invention to provide a novel semiconductor device with an improved titanium polycide gate electrode free from the above problems.
It is a still additional object of the present invention to provide a novel semiconductor device with an improved titanium polycide gate electrode having a reduced sheet resistance which is highly stable.
It is yet an additional object of the present invention to provide a novel semiconductor device with an improved titanium polycide gate electrode having a high stability of lamination structure or shape.
It is still another object of the present invention to provide a novel method of forming a titanium polycide layer free from the above problems.
It is a further object of the present invention to provide a novel method of forming a polycide layer having a reduced sheet resistance which is highly stable.
It is a still further object of the present invention to provide a novel method of forming a polycide layer having a high stability of lamination structure or shape.
It is yet a further object of the present invention to provide a novel method of forming a titanium polycide gate electrode free from the above problems.
It is yet more object of the present invention to provide a nov
McGinn & Gibb PLLC
NEC Corporation
Nelms David
Nhu David
LandOfFree
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