Timing window elimination in self-modifying direct memory...

Details Timing window elimination in self-modifying direct memory... Timing window elimination in self-modifying direct memory...

2000-06-26

2003-09-16

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S023000, C710S025000, C710S026000, C710S028000, C710S065000, C712S034000, C712S036000, C712S038000

Reexamination Certificate

active

06622181

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is digital data processors especially those including direct memory access units which can self-modify their data transfer parameters.
BACKGROUND OF THE INVENTION
In design of microprocessors and particularly digital signal processors (DSP) the need for autonomous data movement via a direct memory access (DMA) controller has become increasingly common. The ability to perform complex data transfers within a memory hierarchy without central processing unit interventions offers substantial system performance benefits by offloading the data movements tasks from the central processing unit. This is particularly helpful for central processing unit which are not natively optimized to control data movement. For example, a digital signal processor might include four to eight parallel functional units, each capable of executing an instruction in a single machine cycle. Of these eight units however, typically only one or two will be capable of controlling memory transfers. Hence, using the central processing unit to perform memory moves is inefficient and degrades system performance. As a consequence, a direct memory access controller becomes a powerful system peripheral.
In order for a direct memory access to be utilized most efficiently, it will generally include one or more channels. A DMA channel generically refers to the context of a memory transaction. Such a context might include the source and destination address of the transaction, a data transfer count, plus any special transfer options that the controller supports. The context of each channel is typically managed by the direct memory access unit and is stored in some storage element. This storage element is typically a RAM or register set. The central processing unit of the system generally has access to these context elements, but will typically access them only for transfer initialization and status monitoring.
FIG. 1
illustrates a channel controller of typical known direct memory access unit. Implementations of direct memory access units may vary widely, but the elementary conventional direct memory access controller channel illustrated in
FIG. 1
is suitable for the purpose of explanation. The major task of the direct memory access controller is to generate the source (SRC) address, the destination (DST) address and the transfer count. Register
100
holds the source address which is updated through multiplexer
103
in the run condition and recirculated via path
105
in the case of a stall. Updating the source address consists of addition with a 1 word address increment to the next address location via adder
102
. Reload parameters and central processing unit data updates are inserted through multiplexer
104
when auto load or central processing unit write operations are activated.
Similarly register
110
holds the destination address which is updated through multiplexer
113
in the run condition and recirculated via path
115
in the case of a stall. Updating the destination address consists of addition with a 1 word address increment to the next address location via adder
112
. Reload parameters and central processing unit data updates are inserted through multiplexer
114
when auto load or central processing unit write operations are activated.
Register
120
holds the data transfer count which is updated through multiplexer
123
in the run condition and recirculated via path
125
in the case of a stall. Updating the data transfer count consists of subtraction with a 1 word address increment to the next transfer count via adder
122
. Reload parameters and central processing unit data updates are inserted through multiplexer
124
when auto load or central processing unit write operations are activated. In addition the run/stall signal is generated from a logical combination of channel exhaust condition (zero data transfer count) and the channel request signal generated external to this block.
A common use of a direct memory access engine is for the maintenance of double buffers. In a double buffering scheme, the central processing unit of the system will own one of the buffers, which it uses to process data. The direct memory access will own the other buffer and will write data to or read data from the buffer. The direct memory access unit is typically driven from a real-time system event. For example, in a capture buffer scheme action is as follows.
In direct memory access writes to buffers, the triggering direct memory access event might be a “ready” signal from an analog-to-digital (A/D) converter, which tells the direct memory access unit that a sample is ready and should be read from the analog-to-digital converter and placed into memory. Each event from the analog-to-digital converter to the direct memory access unit tells the direct memory access unit to move one data word corresponding to an analog sample from the source in the analog-to-digital converter to a destination in one of the double buffers. The direct memory access unit performs this transaction and typically also updates the destination address so that the next sample will be written to the next sequential destination address. Note that decrementing destination addresses and indexed addressing modes are also common. The direct memory access unit will also decrement the data transfer count, so that the end of the data transfer can be detected when the data transfer count reaches zero. The event from the analog-to-digital converter to the direct memory access unit will occur many times during the course of filling one of the buffers in a double buffering scheme.
The typical double buffering technique is illustrated in FIG.
2
. Analog-to-digital converter
200
supplies a data ready signal to direct memory access controller
201
in response to the source address
203
. Direct memory access controller
201
in turn generates the destination addresses for the two banks of capture buffers
204
and
205
. The interleaving of the direct memory access read/write activity with direct memory access idle time
206
and analog-to-digital converter data ready signals
207
is shown in the timing diagram.
At some point in time, the buffers must be switched, such so that the central processing unit can process the newly sampled analog-to-digital data. When the buffers are switched, the central processing unit is given access to the buffer that the direct memory access unit formerly owned and the direct memory access unit assumes ownership of the buffer that the central processing unit formerly owned. In order not to lose any data sample, this switch will occur as a result of an interrupt
210
from direct memory access unit
201
to the central processing unit generated upon occurrence of event
211
when the channel data transfer count has reached zero. This indicatives a full buffer. The interrupt informs the central processing unit that the direct memory access unit has filled a new buffer and that the direct memory access unit intends to assume control of the other buffer so that it can continue capturing the real-time data stream from analog-to-digital converter
200
.
At this point, it is generally necessary that the direct memory access channel parameters be reloaded, since the transfer count is now zero and the destination address has updated to a value no longer in the range of one of the double buffers. The reload of parameters into the direct memory access channel storage can occur via several methods. Historically, this has occurred as a result of the central processing unit performing a series of accesses to the direct memory access unit storage elements during the interrupt service routine in response to the aforementioned interrupt. This operation is also illustrated at times
212
and
213
in FIG.
2
.
While effective in some situations, as the number and complexity of direct memory accesses in a system increase this service requires a greater amount of central processing unit intervention and thus degrades system performance. To combat this performance loss, sop

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