Timing violation debugging inside place and route tool

Details Timing violation debugging inside place and route tool Timing violation debugging inside place and route tool

2008-01-29

2008-01-29

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07325215

ABSTRACT:
A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route tool. The violation display may include (i) a plurality of performance violations for the circuit design and (ii) a plurality of user inputs each associated with one of the performance violations. The layout display may include a layout view of the circuit design. The layout view may highlight at least one of (i) a plurality of cells and (ii) a plurality of networks each along a path related to a particular one of the performance violations identified by a user through the user inputs.

REFERENCES:
patent: 5793643 (1998-08-01), Cai
patent: 6230304 (2001-05-01), Groeneveld et al.
patent: 7069528 (2006-06-01), Kovacs et al.
patent: 2003/0005398 (2003-01-01), Cho et al.
patent: 2006/0271899 (2006-11-01), Tan et al.

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