Timing verifying method

Details Timing verifying method Timing verifying method

2001-04-20

2003-01-14

Crane, Sara (Department: 2811)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S019000

Reexamination Certificate

active

06507936

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method for calculating a delay time in a logic element of a semiconductor integrated circuit and, more particularly, to a timing verifying method for verifying the operational timing of a semicustom LSI such as an ASIC.
In the fabrication of semiconductor integrated circuits, microfabrication technology for elements such as transistors and wires has advanced in recent years.
With the increasing miniaturization of the elements, a delay time in a transistor contained in a logic cell (hereinafter referred to as a cell delay time) has been reduced, while the distance between wires and the width of each of the wires have been reduced. This increases the capacitance between the wires (wire-to-wire capacitance) and the resistance of each of the wires (wire resistance) so that a delay time in each of the wires (hereinafter referred to as a wire delay time) is increased accordingly. As the elements are miniaturized, the proportion of the wire delay time in an overall delay time in an LSI is increased so that accurate estimation of the wire delay time will be more and more important in the future.
When the operational timing of an LSI is verified, a delay time is calculated in consideration of processing variations produced during the fabrication process or variation in temperature, power source, or the like. If timing verification is performed in consideration of a wire delay time, the wire resistance and wire-to-wire capacitance are calculated while assuming variation in the film thickness or width of the wire, the thickness or dielectric constant of an interlayer film, or the like and the wire delay time is calculated by using the wire resistance and wire-to-wire capacitance. For the timing verification, there is used the technique for performing circuit simulation by calculating the wire resistance and wire-to-wire capacitance based on an amount of variation caused in a process varying factor which is determined by the process for fabricating an LSI and which varies at least one of the wire resistance and wire-to-wire capacitance (hereinafter referred to as an amount of process variation).
In the method disclosed in Japanese Unexamined Patent Publication HEI 10-240796 (hereinafter referred to as the conventional timing verifying method), electric characteristics including wire resistance and wire-to-wire capacitance are expressed as a function using an amount of process variation as a parameter. Specifically, a net list of wire resistances and wire-to-wire capacitances which are expressed as a function using, as a parameter, an amount of process variation such as the width or film thickness of each of wires (hereinafter referred to as a functional description net list) is used to calculate the wire resistances and wire-to-wire capacitances by reading a layout configuration of the wires. In the case of verifying the influence of the process varying factor on circuit characteristics, if the layout configuration is read once, a net list of the wire resistances and the wire-to-wire capacitances (hereinafter referred to as an RC net list) is newly generated only by inputting the parameter corresponding to the amount of process variation to the functional description net list. By performing circuit simulation using the RC net list, therefore, the influence of the process varying factor on circuit characteristics can be estimated easily.
Thus, even if the process has been changed or undergone variations, the conventional timing verifying method performs circuit simulation by inputting the parameter corresponding to the amount of process variation to the functional description net list without generating again an RC net list based on the layout configuration. This allows easy prediction of a change in circuit characteristics resulting from changes or variations in the fabrication process.
If the layout configuration has been obtained and the fabrication process is undetermined, the conventional timing verifying method allows the process for implementing desired circuit characteristics to be determined or allows the process to be optimized by repeatedly performing circuit simulation, while diversely varying the definition of the parameter in the functional description net list.
However, since it is necessary for the conventional timing verifying method to repeatedly perform circuit simulation by the number of times corresponding to the number of RC net lists which are generated on a one-by-one basis for the individual amounts of process variation set as the parameters, the time or steps required by timing verification is increased disadvantageously.
SUMMARY OF THE INVENTION
In view of the foregoing, it is therefore an object of the present invention to allow timing verification considering process variation to be performed efficiently.
A first timing verifying method according to the present invention assumes a timing verifying method for verifying an operational timing of a semiconductor integrated circuit composed of a plurality of cells having logic functions, the plurality of cells being placed in the semiconductor integrated circuit and having respective terminals connected by wires, the method comprising: a variation delay time calculating step of calculating at least two variation delay times by performing at least twice each of a first sub-step of setting, for a process varying factor which is determined by a process for fabricating the semiconductor integrated circuit and which varies at least one of resistance of each of the wires and capacitance between each of the wires and the wire adjacent thereto, an amount of process variation which is an amount of variation caused in the process varying factor, a second sub-step of calculating the resistance of the wire and the capacitance between the wires based on the amount of process variation and on a layout configuration of the wires, and a third sub-step of calculating a first delay time in the wire and a second delay time in the driving cell of the plurality of cells which drives the wire by using the resistance of the wire and the capacitance between the wires that have been calculated, while varying the amount of process variation, each of the at least two variation delay times being composed of the first delay time and the second delay time; a delay data synthesizing step of generating a synthesized delay time which determines operation characteristics of the semiconductor integrated circuit based on the at least two variation delay times; and a logic simulation step of performing logic simulation of the semiconductor integrated circuit by using the synthesized delay time.
In accordance with the first timing verifying method, the at least two variation delay times corresponding to the different amounts of process variation, i.e., to the different process varying conditions are calculated, the synthesized delay time which determines the operation characteristics of the semiconductor integrated circuit is generated based on the at least two variation delay times, and then the logic simulation of the semiconductor integrated circuit is performed by using the synthesized delay time. This allows the calculation of the variation delay times corresponding to the process varying conditions to be performed independently of the logic simulation of the semiconductor integrated circuit and allows the logic simulation to be performed by using only the synthesized delay time generated based on the at least two variation delay times. Since it is no more necessary to repeatedly perform logic simulation or circuit simulation with respect to the plurality of process varying conditions, timing verification considering process variation can be performed efficiently.
In the first timing verifying method, the delay data synthesizing step preferably includes the step of determining, as the synthesized delay time, the maximum or minimum one of the at least two variation delay times.
If the maximum one of the variation delay times is selected as the synthesized delay time, the arrangement all

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