Timing verifier for MOS devices and related method

Details Timing verifier for MOS devices and related method Timing verifier for MOS devices and related method

1998-12-10

2002-10-29

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06473888

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention.
The present invention relates to timing verification tools used for analyzing circuit designs. In particular, it relates to a tool for determining accurate, analytic expressions for the capacitance and charge of MOS devices in a circuit.
2. Discussion of the related art.
Circuit verification is a significant part of analyzing a design of a circuit. It is significantly more economical to ensure that the circuit will operate as intended prior to production. Timing verification is a portion of the circuit verification process. Timing verification is used to identify all critical and race paths through a circuit. Critical paths are paths through which a signal passes more slowly than other paths. In race paths, the signals pass more quickly. Timing verification has become increasingly more important for the design of CMOS circuits. As CMOS circuits on a chip have become more complex, the complexity for verifying timing has also increased. Also, as chips are designed to operate at higher speeds, timing verification must be more accurate. Thus, accurate timing verification of complex structures is a principal part of the design process for circuits.
A variety of tools are available for timing verification. These tools have different speeds for verification and different accuracy of the results. The most significant concern for a circuit designer is that a functional violation will go undetected during timing verification, i.e. that an error will not be found during the verification process. If a violation is missed by the timing verifier, the circuit will pass to the silicon where errors become more difficult and more costly to uncover and resolve.
One type of timing verification tool is computerized circuit simulators, such as SPICE. With SPICE, the circuit is modeled within the computer. The program simulates operation of an entire circuit which is represented as a set of connected elements. Certain assumptions are made regarding the inputs. The program then determines the value of signals at all of the points within the circuit at spaced time intervals. While SPICE and other circuit simulators provide very accurate timing information on a circuit, they are also extremely slow. They operate with small time segments and make many calculations for each time segment to determine the signal values at each of the many nodes in a circuit. This slow speed inhibits their application as useful timing verification tools for an entire circuit. Therefore, other timing verification tools have been created which use simpler models of a circuit. These other tools provide much faster speeds with a loss of accuracy. Since accuracy decreases with such tools, a circuit designer will often use the simpler, quicker tools just to determine potential critical or race paths, or paths which may induce a functional violation. Once certain paths are identified, they will be checked more accurately using SPICE or a similar circuit simulator, to determine whether any changes need to be made to the circuit.
With a timing verification tool, it is most important not to miss any violations. A missed violation will result in an erroneous circuit, which may not be detected until much later. However, the number of false violations should also be minimized. As the number of detected violations increases, the time to accurately check each detected violation also increases. With many false violations being reported by the timing verifier, the time for checking the circuit becomes needlessly large. Therefore, a need exists for a timing verification tool which quickly and accurately estimates minimum and maximum delay times, while erring on the pessimistic side in order to insure that no violations are missed.
Traditionally, the delays through MOSFETs have been calculated by treating them as a resistance-capacitance (RC) structure. By using a model of the corresponding RC structure for a MOS device, the Miller capacitance can be used to determine the maximum and minimum values for delays. The Miller capacitance is used because it is easy to calculate and represents a worst case scenario. However, the difference between delays using such models differs significantly from actuality. Such inaccuracies result in large numbers of false violations which need to be checked. Therefore, a need exists for a timing verification tool which more accurately reflects delays and capacitances within the circuit.
SUMMARY OF THE INVENTION
The present invention overcomes many of the deficiencies with the prior art by providing a timing verification tool which more accurately models capacitances or charges in MOSFET devices. The present invention includes a computer-based system for generating timing models and charge models for each node in the circuit. The models are used to estimate delays within the circuit. To create capacitance models, the system represents a set of MOSFETs within certain defined structures. The system then runs simulations using SPICE or a similar circuit simulator, to determine data points for capacitances or charges at specific locations within the structures. The set of data generated in the simulations is then used to determine charge models for each point in the various structures using curve fitting techniques. The charge models represent the charge based upon the width and length of the MOSFET under the operating conditions for the circuit. The models can then be used in a timing verifier for calculating capacitance or charge in determining delays.


REFERENCES:
patent: 4924430 (1990-05-01), Zasio et al.
patent: 5452225 (1995-09-01), Hammer
patent: 5548526 (1996-08-01), Misheloff
patent: 5559715 (1996-09-01), Misheloff
patent: 5748489 (1998-05-01), Beatty et al.

Affiliated with

Also associated with

Rating

Timing verifier for MOS devices and related method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing verifier for MOS devices and related method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing verifier for MOS devices and related method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2990956