Timing verification method for semiconductor integrated circuit

Details Timing verification method for semiconductor integrated circuit Timing verification method for semiconductor integrated circuit

2007-12-11

2007-12-11

Wachsman, Hal (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system

Statistical measurement

C702S125000, C702S079000, C702S069000, C702S189000, C713S500000, C713S503000, C716S030000, C714S731000, C714S744000

Reexamination Certificate

active

11495778

ABSTRACT:
Initially, non-uniformity of statistical skews between a plurality of clock output terminal pairs is calculated. Next, a partial circuit driven by a clock output terminal pair having each skew distribution is extracted from an integrated circuit. Next, a second statistical timing characteristic which is a maximum value in the partial circuit is obtained from a first statistical timing characteristic of signal paths included in the extracted partial circuit. Next, timing verification for the integrated circuit is performed using the second statistical timing characteristics corresponding to the respective statistical clock skews.

REFERENCES:
patent: 6915497 (2005-07-01), Kitahara
patent: 7075336 (2006-07-01), Kojima et al.
patent: 2004/0167756 (2004-08-01), Yonezawa
patent: 10-301982 (1998-11-01), None
patent: 2967759 (1999-08-01), None
patent: 2005-259107 (2005-09-01), None
patent: WO 03/060776 (2003-07-01), None
K.A. Bowman et al., “Impact ofWithin-DieParameter Fluctuations on Future Maximum Clock Frequency Distributions,” Custom Integrated Circuits Conference (2001), no month.

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