Timing verification, automated multicycle generation and...

Details Timing verification, automated multicycle generation and... Timing verification, automated multicycle generation and...

2006-01-03

2006-01-03

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06983437

ABSTRACT:
A method for generating consistent functional and timing definitions. The method includes providing a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design, transforming the common source description to a functional definition, monitoring a functional simulation of the integrated circuit chip design using the functional definition, transforming the common source description to a timing definition, and performing a timing analysis of the integrated circuit chip design using the timing definition.

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patent: 6877139 (2005-04-01), Daga

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