Timing variation aware compilation

Details Timing variation aware compilation Timing variation aware compilation

2006-08-09

2008-12-23

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07469394

ABSTRACT:
Design compilation software uses statistical analysis techniques to account for variations in device attributes. A compilation phase determines statistical attributes of edges and other elements of device, such as the mean and variance values of attributes. A compilation phase evaluates the suitability of a potential configuration of the device using a cost function. The cost function can be based on one or more independent criteria of the design, such wiring or routing costs, timing costs, and power consumption costs. The compilation phase can include clustering, placement, and routing of the design. One or more of the cost function criteria can include statistical attributes of the device. The compilation software can use statistical attributes of the device to predict device yields for a design. The compilation software can also predict device yields of a design using devices of different speed bin classifications.

REFERENCES:
patent: 6901564 (2005-05-01), Stine et al.
patent: 7181717 (2007-02-01), Singh et al.
patent: 7308381 (2007-12-01), Yonezawa et al.

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