Timing reference circuit for bitline precharge in memory arrays

Details Timing reference circuit for bitline precharge in memory arrays Timing reference circuit for bitline precharge in memory arrays

1995-08-30

1996-10-08

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36518911, G11C 700

Patent

active

055638317

ABSTRACT:
In memory arrays using MOSFET technology the bitlines and inverse bitlines must be precharged to an initial value before the beginning of the active period of the memory cycle. The time required to precharge the bitlines and inverse bitlines is not a useful part of the memory cycle and it is desirable to keep the precharge time as low as possible. This invention provides circuits and a method of maintaining a higher voltage at the gates of the isolation MOSFETs in the memory array during the precharge period and returning the voltage to a lower level before the end of the inactive period, thereby significantly reducing the precharge time.

REFERENCES:
patent: 4787066 (1988-11-01), Leuschner
patent: 5361237 (1994-11-01), Chishiki
patent: 5367489 (1994-11-01), Park

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