Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-08-23
2005-08-23
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06934922
ABSTRACT:
Method to determine path timing to and from an embedded device is described. More particularly, clock-to-output delays, interconnects and interconnect logic delays, and setup and hold times for input and output paths from a microprocessor core and a memory controller are obtained and determined, as applicable. These times are assembled in a spreadsheet for associating with respective signals. Times for each of the signals are totaled to determine respective path delays for comparison with a target clock period.
REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4855669 (1989-08-01), Mahoney
patent: 5072418 (1991-12-01), Boutaud et al.
patent: 5142625 (1992-08-01), Nakai
patent: RE34363 (1993-08-01), Freeman
patent: 5274570 (1993-12-01), Izumi et al.
patent: 5311114 (1994-05-01), Sambamurthy et al.
patent: 5339262 (1994-08-01), Rostoker et al.
patent: 5347181 (1994-09-01), Ashby et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5457410 (1995-10-01), Ting
patent: 5473267 (1995-12-01), Stansfield
patent: 5500943 (1996-03-01), Ho et al.
patent: 5504738 (1996-04-01), Sambamurthy et al.
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5535223 (1996-07-01), Horstmann et al.
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5543640 (1996-08-01), Sutherland et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5552722 (1996-09-01), Kean
patent: 5572717 (1996-11-01), Pedersen
patent: 5574930 (1996-11-01), Halverson, Jr. et al.
patent: 5574942 (1996-11-01), Colwell et al.
patent: 5581745 (1996-12-01), Muraoka
patent: 5600845 (1997-02-01), Gilson
patent: 5652904 (1997-07-01), Trimberger
patent: 5671355 (1997-09-01), Collins
patent: 5705938 (1998-01-01), Kean
patent: 5732250 (1998-03-01), Bates et al.
patent: 5737631 (1998-04-01), Trimberger
patent: 5740404 (1998-04-01), Baji
patent: 5742179 (1998-04-01), Sasaki
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5748979 (1998-05-01), Trimberger
patent: 5752035 (1998-05-01), Trimberger
patent: 5760607 (1998-06-01), Leeds et al.
patent: 5809517 (1998-09-01), Shimura
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5874834 (1999-02-01), New
patent: 5889788 (1999-03-01), Pressly et al.
patent: 5892961 (1999-04-01), Trimberger
patent: 5914616 (1999-06-01), Young et al.
patent: 5914902 (1999-06-01), Lawrence et al.
patent: 5933023 (1999-08-01), Young
patent: 5970254 (1999-10-01), Cooke et al.
patent: 6011407 (2000-01-01), New
patent: 6020755 (2000-02-01), Andrews et al.
patent: 6026481 (2000-02-01), New et al.
patent: 6096091 (2000-08-01), Hartmann
patent: 6154051 (2000-11-01), Nguyen et al.
patent: 6163166 (2000-12-01), Bielby et al.
patent: 6172990 (2001-01-01), Deb et al.
patent: 6178541 (2001-01-01), Joly et al.
patent: 6181163 (2001-01-01), Agrawal et al.
patent: 6211697 (2001-04-01), Lien et al.
patent: 6242945 (2001-06-01), New
patent: 6272451 (2001-08-01), Mason et al.
patent: 6279045 (2001-08-01), Muthujumaraswathy et al.
patent: 6282627 (2001-08-01), Wong et al.
patent: 6301696 (2001-10-01), Lien et al.
patent: 6343207 (2002-01-01), Hessel et al.
patent: 6353331 (2002-03-01), Shimanek
patent: 6356987 (2002-03-01), Aulas
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6434735 (2002-08-01), Watkins
patent: 6460172 (2002-10-01), Insenser Farre et al.
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6483342 (2002-11-01), Britton et al.
patent: 6507942 (2003-01-01), Calderone et al.
patent: 6510548 (2003-01-01), Squires
patent: 6518787 (2003-02-01), Allegrucci et al.
patent: 6519753 (2003-02-01), Ang
patent: 6522167 (2003-02-01), Ansari et al.
patent: 6532572 (2003-03-01), Tetelbaum
patent: 6539508 (2003-03-01), Patrie et al.
patent: 6541991 (2003-04-01), Hornchek et al.
patent: 6578174 (2003-06-01), Zizzo
patent: 6587995 (2003-07-01), Duboc et al.
patent: 6588006 (2003-07-01), Watkins
patent: 6601227 (2003-07-01), Trimberger
patent: 6604228 (2003-08-01), Patel et al.
patent: 6611905 (2003-08-01), Grundon et al.
patent: 6611951 (2003-08-01), Tetelbaum et al.
patent: 6675272 (2004-01-01), Ware et al.
patent: 6686769 (2004-02-01), Nguyen et al.
patent: 2001/0049813 (2001-12-01), Chan et al.
patent: 2003/0062922 (2003-04-01), Douglass et al.
patent: 2003/0097541 (2003-05-01), Abrosimov et al.
patent: 0315275 (1989-10-01), None
patent: 0 905 906 (1999-03-01), None
patent: 1 235 351 (2002-08-01), None
patent: WO 93 25968 (1993-12-01), None
Cary D. Synder and Max Baron; “Xilinx's A-to-Z System Platform”; Cahners Microprocessor; The Insider's Guide to Microprocessors Hardware; Microdesign Resources; Feb. 6, 2001; pp. 1-5.
Sayfe Kiaei et al., “VLSI Design of Dynamically Reconfigurable Array Processor-Drap,” IEEE, Feb. 1989, pp. 2484-2488, V3.6, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Vason P. Srini, “Field Programmable Gate Array (FPGA) Implementation of Digital Systems: An Alternative to ASIC,” IEEE, May 1991, pp. 309-314, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
G. Maki et al., “A Reconfigurable Data Path Processor,” IEEE, Aug. 1991, pp. 18-4.1 to 18-4.4, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Jacob Davidson, “FGPA Implementation of Reconfigurable Microprocessor,” IEEE, Mar. 1993, pp. 3.2.1-3.2.4, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Christian Iseli et al., “Beyond Superscaler Using FPGA's,” IEEE, Apr. 1993, pp. 486-490, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
P.C. French et al.,“A Self-Reconfiguring Processor,”; IEEE, Jul. 1993, pp. 50-59, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Christian Iseli et al., “Spyder: A Reconfigurable VLIW Processor Using FPGA's,” IEEE, Jul. 1993, pp. 17-24, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Michael J. Wirthlin et al., “The Nano Processor: A Low Resource Reconfigurable Processor,” IEEE, Feb. 1994, pp. 23-30, IEEE, 3 Park Avenue, 17 Floor, New York, NY 10016-5997.
William S. Carter, “The Future of Programmable Logic and its Impact on Digital System Design,” Apr. 1994, IEEE, pp. 10-16, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
André Dehon, “DPGA-Coupled Microprocessors: Commodity ICs for the Early 21st Century,”IEEE, Feb. 1994, pp. 31-39, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Osama T. Albaharna, “Area & Time Limitations of FPGA-Based Virtual Hardware,” IEEE, Apr. 1994, pp. 184-189, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
U.S. Appl. No. 10/043,769, filed Jan. 9, 2002, Schultz.
U.S. Appl. No. 10/001,871, filed Nov. 19, 2001, Douglass et al.
U.S. Appl. No. 09/991,412, filed Nov. 16, 2001, Herron et al.
U.S. Appl. No. 09/991,410, filed Nov. 16, 2001, Herron et al.
Xilinx, Inc.,“The Programmable Logic Data Book,” 1994, Revised 1995, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc.,“The Programmable Logic Data Book,” 1994, Revised 1995, pp 2-109 to 2-117, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Xilinx, Inc.,“The Programmable Logic Data Book,” 1994, Revised 1995, pp 2-9 to 2-18; 2-187 to 2-199, Xilinx, Inc., 2100 Logic Drive, San Jose, CA. 95124.
Christian Iseli et al., “AC++ Compiler for FPGA Custom Execution Units Synthesis,” 1995, pp. 173-179, IEEE, 3 Park Avenue, 17 Floor, New York, NY 10016-5997.
International Business Machines,“PowerPC 405 Embedded Processor Core User Manual,” 1996, 5TH Ed., pp. 1-1 to X-16, International Business Machines, 1580 Rout 52, Bldg. 504, Hopewell Junction, NY 12533-6531.
Yamin Li et al., “Aizup-A Pipelined Processor Design & Implementation on Xilinx FPGA Chip,” IEEE, Sep. 1996, pp 98-106, 98-106, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Ralph D. Wittig et al., Onechip: An FPGA Processor With Reconfigurable Logic, Apr. 17, 1996, pp 126-165, IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Xilinx, Inc.,“The Programmable Logic Data Book,” Jan. 27, 1
Garbowski Leigh M.
Kanzaki Kim
Webostad W. Eric
Xilinx , Inc.
LandOfFree
Timing performance analysis does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Timing performance analysis, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing performance analysis will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3494892