Timing path detailer

Details Timing path detailer Timing path detailer

2002-10-30

2004-12-21

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06834379

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of integrated circuit development software, and particularly to timing software.
2. Description of the Related Art
Static timing analysis tools are used to estimate the delays on various timing paths through digital circuit designs. The resulting timing reports are analyzed by the designers to identify timing paths in the design which do not meet the timing goals of the digital circuit, and the designers attempt to change the design so that the design will meet the timing goals.
More recently, digital circuit designs (e.g. designs to be fabricated on a single integrated circuit) have increased in size and complexity as the number of transistors that may be fabricated on a single integrated circuit has increased. As the size of the design has increased, the size has exceeded the capability of various timing analysis tools to analyze the design in its entirety. Designers have responded by dividing the circuit designs into partitions, each of which can be handled by the timing analysis tools (and other integrated circuit design tools such as synthesis tools, layout tools, etc.). As used herein, a partition is a representation of a portion of the overall circuit, and has defined inputs and outputs. The inputs may be sourced by other partitions, or may be inputs of the overall circuit. The outputs may be supplied to other partitions, may be outputs of the overall circuit, or both.
FIG. 1
is a block diagram illustrating a portion of one embodiment of a design flow that includes timing analysis. Once the circuit design has been divided into one or more partitions, the designer may code a register-transfer level (RTL) description of each partition (reference numeral
10
). Any hardware design language (HDL) may be used as the language for the RTL description (e.g. VHDL, Verilog, etc.). The RTL description may comprise one or more files per partition, as desired.
The designer may choose to use a synthesis tool to synthesize the RTL description to a netlist (reference numeral
12
). The synthesis tool takes the RTL description and a library of cells (predesigned circuits which have one or more inputs and produce one or more outputs as a specified function of one or more inputs) and generates a netlist of cells, linked together in such a way as to provide the functionality described in the RTL description. On the other hand, the designer may choose to design the circuits manually, using a circuit schematic/schematic capture tool (reference numeral
14
). The designer may use a combination of circuit schematic design and synthesis for a given partition.
The resulting netlists and schematic capture data may be provided to a timing analysis tool to estimate the timing of the design (i.e. to estimate whether or not the design will meet timing requirements for the circuit to operate at a desired clock frequency) (reference numeral
16
). Based on the timing results, the designer may modify the RTL description and/or the circuit schematics to improve the timing (illustrated in
FIG. 1
with the dotted lines from the timing analysis (reference numeral
16
) to the RTL coding (reference numeral
10
) and the circuit schematics (reference numeral
14
)). At the point illustrated by reference numeral
16
, delay from the nets interconnecting the cells and other circuitry may be estimated (since the layout has not yet been performed) rather than extracted.
At some point, the estimated timing calculated at reference numeral
16
may be near the timing goals for the integrated circuit, and the layout of the netlists may be performed (reference numeral
18
). Alternatively, layout work may start in parallel with timing analysis, or may be performed before any timing analysis is performed, as desired. Generally, the layout includes placing the cells called out in the netlist into physical positions within the integrated circuit layout, and routing the nets which interconnect the cells using the wiring layers of the integrated circuit layout. The circuit schematics produced using the circuit schematic tools may already be laid out within the circuit, but may be placed within the overall layout and the inputs and outputs of the circuit may be connected to nets, similar to the cells.
The timing analysis tool may be executed again (reference numeral
20
), using wire delays for the nets extracted from the integrated circuit layout. If timing goals are still not met, additional layout work, RTL coding, or schematic work may be used to improve timing (dotted lines from reference numeral
20
to reference numerals
10
,
14
, and
18
). Once the timing goals are met, the design flow may continue toward fabricating the integrated circuit (not shown).
One embodiment of an exemplary circuit
30
is shown in
FIG. 2
, having multiple partitions (e.g. partition A
32
A, partition B
32
B, and partition C
32
C illustrated in FIG.
2
). Various timing paths are illustrated in
FIG. 2
within the partitions
32
A-
32
C. The direction of signal flow in
FIG. 2
is from left to right. Generally, a timing path is a path through various circuitry in a partition (or among multiple partitions). The timing path may have an associated delay estimated by a timing analysis tool. The delay may or may not be short enough to meet the timing goals of the circuit
30
.
In
FIG. 2
, various net names (that is, names used to represent nets in the circuit, wherein a net is an interconnecting signal that may be implemented with conductors on the integrated circuit) are illustrated as various letters. Capital letters are net names that are either partition inputs, partition outputs, or state points (controlled by clocks). Lower case letters illustrate net names that are the output of combinatorial logic circuits within the paths. Thus, in
FIG. 2
, the partition
32
A includes a timing path
34
A from a state point W through nets x and y to an output A (which is an input to the partition
32
B). The partition
32
B includes a timing path
34
B from the input A through nets b and c to the state point D and continuing through nets e and f to an output G. Additionally, a timing path
34
C is shown in the partition
34
C from the input A through nets h, i, j, and k to the output G. Finally, a timing path
34
D is shown in the partition
32
C from the input G through nets l, m, n, and o to a state point P and continuing to an output Q. Generally, a state point is any point at which state may be captured according. to a clock (e.g. a flop, register, latch, etc.). The timing paths
34
A,
34
B, and
34
D together form a global timing path in the circuit
30
, as do the timing paths
34
A,
34
C, and
34
D.
A timing analysis of each of the timing paths
34
A-
34
D would include the delays between each net in the path, thus supplying the designer with details permitting the rapid identification of circuitry which may be changed to improve the overall timing of the paths. However, to analyze the global timing paths in the circuit
30
, a timing analysis of the circuit
30
is needed. While the timing paths
34
A-
34
D may each individually appear to be short, a global timing path formed from the timing paths may not meet timing goals. As mentioned above, a timing analysis of the circuit
30
may be too large to perform using the detailed timing paths within each partition
32
A-
32
C. A detailed timing path includes the intermediate details of delays through circuitry within a partition
32
A-
32
C. On the other hand, an abstract model of each partition may be generated. The abstract model may eliminate some of the details from the detailed timing paths to generate corresponding abstracted timing paths. Thus, an abstracted timing path is a timing path which represents the delay of the timing path but which omits at least some details of the timing path.
For example, in some embodiments, an abstracted timing path may retain partition inputs, outputs, and state points. The abstracted timing path may include delays between the inputs, outputs, and state p

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