Timing optimization and timing closure for integrated...

Details Timing optimization and timing closure for integrated... Timing optimization and timing closure for integrated...

2001-09-05

2002-11-26

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06487705

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a timing model for an integrated circuit. More specifically, the present invention relates to method for developing an integrated circuit design to meet timing specifications.
2. Description of the Related Art
Digital circuits, no matter how complex, are composed of a set of building blocks. These blocks can be basic gates, memory cells or other structures. But the majority of digital circuits are composed of gates or combinations of gates. Gates are combinations of high-speed electronic switches. Memory cells are composed of basic logic gates. A flip-flop, for example, can be considered as a memory cell. A microprocessor is a central processing unit of a computer or other device using thousands (or millions) of gates, flip-flops and other memory cells.
Sub-micron designs of integrated circuit chips require accurate timing analysis to prevent operational errors. These timing errors create operational errors which prevent a design, or a manufactured chip, from accomplishing its intended purpose. It is known to use available software tools to design an integrated circuit and to model the functions and timing of the signals on the circuit.
It is known to manufacture an integrated circuit using conductors separated by a semi-conductor. Circuits are fabricated on a semiconductor by selectively altering the conductivity of the semiconductor material. Various conductivity levels correspond to elements of a transistor. Transistors, diodes, resistors, and small capacitors are formed on small chips of silicon. Individual components are interconnected by aluminum or gold wiring patterns. Integrated circuits are then mounted on etched circuit boards which are used to assemble electronic systems such as personal computers and other data processing equipment.
It is known to use commercially available software to model certain features of integrated circuits. For example Verilog, originally designed by Gateway Design Automation in 1985, is a hardware description language (HDL) most predominantly used in the United States. Verilog was made available to the public in 1990 and has been adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE).
Other electronic design automation (EDA) tools are available to simulate logic of a processor. As electronic design tools became more popular, vendors began to provide enhanced functions. EDA tools are now used to drive synthesis, timing, simulation, test and other tools. Other vendors of EDA tools are: Cadence Corporation, Providence, R.I.; Mentor Graphics, Oreg.; Snyopsys, Calif.; and Snytest Technologies, Inc. California. These products are listed as examples only, other manufactures use proprietary tools for the same purpose. Electronic design automation (EDA) tools were originally designed to simulate logic. As electronic design tools became more popular, vendors began to provide enhanced functions. EDA tools are now used to drive synthesis, timing, simulation, test and other tools. Other vendors of EDA tools are: Cadence Corporation, Providence R.I.; Mentor Graphics, Wilsonville, Oreg.; Snyopsys, Mountainview, Calif.; and Snytest Technologies, Inc., Sunnyvale, Calif. These corporations are listed as examples only, other manufactures use proprietary tools for the same purpose. For example the Silicon Ensemble tool provided by Cadence places and routes wires on the integrated circuit driven by timing constraints.
Register transfer level synthesis (sometimes referred to as “RTL synthesis” or simply “synthesis”), placement and routing are essential steps to transform a formal functional description of a digital circuit into a design which can be manufactured. Currently available software tools can produce a design according to synthesis, placement and routing. Capacitance, resistance and inductance (collectively referred to as electrical parasitics) resident in the blocks and interconnections influence the timing behavior of the integrated circuit being designed. Thus, neither the electrical performance of the circuit nor the timing behavior are specified in the design.
Referring to
FIG. 1
, the steps shown are directed to design a circuit with the desired electrical performance and within the specified timing parameters (e.g., correct operation at a given clock frequency and manufactured with a specific die size). The design process consists of subsequent design steps A, B, C . . . M. As further discussed below, design step A is exemplified by RTL synthesis. Design step B is exemplified by placement,
120
. Design step C is exemplified by routing,
130
.
It will be noted that the variable identifier “M” is used in FIG.
2
and
FIG. 4
to more simply designate the final step in a series of steps. (Similarly, variable identifier “N” is used in
FIGS. 3B and 5
for the same purpose.) The use of such variable identifiers does not require that each series of elements has the same number of elements as another series delimited by the same variable identifier. Rather, in each instance of use, the variable identified by “M” may hold the same or a different value than other instances of the same variable identifier. Similarly, in each instance of use, the variable identified by “N” may hold the same or a different value than other instances of the same variable identifier.
Design Step A, RTL synthesis
110
, transforms an abstract behavior description of an electronic circuit into a functionally equivalent structural description. The behavior description is represented in design database A,
114
. The structural description is represented in design database B,
124
. The components from which the structural description is built are selected from a library. This library has been characterized to contain information necessary to perform embedded timing analysis for the electronic circuit. Referring briefly to
FIG. 2
, the library contains a timing model for each arc of the component, timing model for arc
260
. A timing arc denotes the abstract specification of a timing measurement. (An example of a timing measurement is a delay from rising edge at pin Y to a falling edge at pin Z.) The library also contains at least one parasitic estimation model,
295
(described in
FIG. 2
, below). The purpose of embedded timing analysis is to enable optimization within
110
until the electronic circuit meets the desired timing specification. Referring briefly to
FIG. 2
, the desired timing specification is represented by timing constraints and exceptions from designer,
250
. Slack distribution A,
118
, provides a representation of the result of embedded timing analysis.
Design step B, placement
120
, specifies a physical location for each component of the electronic circuit on a silicon die, printed circuit board, etc., based on the structural electronic circuit information in design database B,
124
. The result of design step B is represented in design database C,
134
. Placement also contains embedded timing analysis and optimization. The timing model for arc,
260
, is similar as for design step A. However, parasitic estimation model,
295
, is different. In design step A, parasitic estimation was based on structural circuit description only, whereas in design step B placement information is available for more accurate parasitic estimation. Slack distribution B,
128
, again provides a representation of the result of embedded timing analysis.
Design step C, routing,
130
, specifies physical interconnect routes between the individual components, based on the structural electronic circuit information and placement information in design database C,
134
. The result of design step C is represented in reference design database,
140
. Routing also contains embedded timing analysis and optimization. The timing model for arc,
260
, is similar as for design step A and B. However, the parasitic estimation model,
295
, is different. The estimation model is more accurate than in design step A and B, because specific route information is available. Specific

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