Timing of a circuit design

Details Timing of a circuit design Timing of a circuit design

2011-03-29

2011-03-29

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

Reexamination Certificate

active

07917881

ABSTRACT:
Improving the timing and/or yield of a circuit design is disclosed. Timing and yield improvements are often competing objectives in circuit design since timing improvements typically result from reducing capacitive couplings and yield improvements typically increase capacitive couplings. Trade-offs between timing and yield improvements are consequently part of the circuit design and/or optimization process.

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Mitch Heins, Pyxis Technology, EE Times Online, In the Eye of the DFM/DFY Storm, May 25, 2007, http://www.eetimes.com/showArticle.jhtml;jsessionid=5L54GMGMWMJKOQSNDLOSKHSCJUNN2JVN?articleID=199702741.
Wilbur Luo, EE Times Online, A Balanced Approach to Chip Optimization, Apr. 24, 2006, http://www.eetimes.com/showArticle.jhtml;jsessionid=5L54GMGMWMJKOQSNDLOSKHSCJUNN2JVN?articleID=185303804.
Laura Peters, Semiconductor International, Demystifying Design-for-Yield, Jul. 1, 2004, http://www.semiconductor.net/article/CA430963.html.
Jason Cong et al., Advanced Routing Techniques for Nanometer IC Designs, ICCAD 2006 Routing Tutorial.

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