Timing model extraction by timing graph reduction

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C716S030000, C716S030000

Reexamination Certificate

active

06928630

ABSTRACT:
Disclosed is a method and system for extracting a timing model. One disclosed approach to extract a timing model is by reducing the timing graph. Original timing behavior is preserved in the timing model including arrival times, slew times, timing violations and even latch time borrowing that is independent of clock waveforms. Also, original timing constraints can be captured in the model and be applied automatically when the model is used. Anchor points are automatically identified and retained to obtain a model that is smaller than the original netlist.

REFERENCES:
patent: 5469367 (1995-11-01), Puri et al.
patent: 5535145 (1996-07-01), Hathaway
patent: 5581473 (1996-12-01), Rusu et al.
patent: 5790830 (1998-08-01), Segal
patent: 5796621 (1998-08-01), Dudley et al.
patent: 5923564 (1999-07-01), Jones, Jr.
patent: 6158022 (2000-12-01), Avidan
patent: 6421818 (2002-07-01), Dupenloup et al.
patent: 6539536 (2003-03-01), Singh et al.
patent: 6591407 (2003-07-01), Kaufman et al.
patent: 6609233 (2003-08-01), Foltin et al.
patent: 2003/0009734 (2003-01-01), Burks et al.
patent: 2004/0078767 (2004-04-01), Burks et al.
patent: WO 01/08028 (2001-02-01), None
Moon, C.W. et al. “Timing Model Extraction of Hierarchical Blocks by Graph Reduction” Proceedings 2002 Design Automation Conference (IEEE Cat. No. 02CH37324) Proceedings of 39thDesign Automation Conference, New Orleans, LA, USA, Jun. 10-14, 2002, pp. 152-157.
Cherry, James J., “Pearl: A CMOS Timing Analyzer”, 25thACM/IEEE Design Automation Conference, 1988, pp. 148-153.
Venkatesh, S.V. et al., “Timing Abstraction of Intellectual Property Blocks”, IEEE 1997 Custom Integrated Circuits Conference, 1997, pp. 99-102.
McDonald, Clayton B. et al., “A Symbolic Simulation-Based Methodology for Generating Black-Box Timing Models of Custom Macrocells”, ICCAD, 2001, pp. 501-506.
Visweswariah, Chandu el al., “Formulation of Static Circuit Optimization with Reduced Size, Degeneracy and Redundancy by Timing Graph Manipulation”, ICCAD, 2000, pp. 244-251.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Timing model extraction by timing graph reduction does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Timing model extraction by timing graph reduction, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Timing model extraction by timing graph reduction will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3520519

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.