Timing method and apparatus for digital logic circuits

Details Timing method and apparatus for digital logic circuits Timing method and apparatus for digital logic circuits

2006-10-03

2006-10-03

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S500000

Reexamination Certificate

active

07117384

ABSTRACT:
A differentiated granularity timing apparatus and a method to provide various flexible timing granularities without requiring much memory space and complex circuit design are disclosed. The differentiated granularity timing apparatus of the present invention comprises a differentiated granularity timing unit, a comparing unit, an adder and a buffer. The buffer is for storing a time value. The comparing unit further comprises a comparator and a plurality of predetermined time interval values stored therein. The comparator is for outputting a control signal according to the time value. The differentiated granularity timing unit further comprises a multiplexer and a plurality of timers. Each timer is for providing a timing signal with different timing granularities respectively. The multiplexer is for outputting one of the timing signals with the corresponding timing granularity according to the control signal.

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