Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2000-11-21
2002-04-30
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S189050, C365S205000
Reexamination Certificate
active
06381181
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a self-latching data circuit, and more particularly to a self-latching data circuit with time independent current comparison and low power draw.
A flash memory is a type of non-volatile memory cell that is electrically reprogrammable. Flash memories are used in various electronic systems such as cellular telephones, personal data assistants (PDA), and notebook computers. The flash memories typically store boot up code that is executed at power up of the electronic system and a program code that is executed during the operation of the electronic system.
At power up, the data from the flash memory is loaded into a volatile memory, such as random access memory. Conventional memory systems load data from a memory cell into a latch circuit on a first transition of an enable signal and then latch the data in the latch circuit and disconnect the latch circuit from the memory cell in response to a second transition of the enable signal. Such conventional memory systems require that the width of the enable signal account for the time required to load before latching the data. Consequently, the conventional memory systems use a timer to determine the pulse width of the enable signal. This is problematic because the power signal is very noisy during power up which can disrupt the loading of the data.
FIG. 3
is a schematic diagram of a conventional memory cell. The conventional memory cell
300
comprises first and second inverters
302
and
304
, respectively, first and second n-channel metal oxide semiconductor field effect transistors (NMOS transistors)
306
and
308
, respectively, and first and second fuses
310
and
312
, respectively. The first and second inverters
302
and
304
are cross-coupled as a latch circuit so that the output of the first inverter
302
is applied to the input of the second inverter
304
, and the output of the second inverter
304
is applied to the input of the first inverter
302
. The first and second NMOS transistors
306
and
308
couple the respective fuses
310
and
312
to the input of the respective inverters
302
and
304
. An enable signal from a timer
314
is applied to the gates of the NMOS transistors
306
and
308
which couples the data stored in the fuses
310
and
312
to the latch circuit formed of the inverters
302
and
304
. The enable signal is kept high for a predetermined time in order to allow the power of the circuit to reach a steady state and for the inverters
302
and
304
to latch the data from the fuses
310
and
312
. After the predetermined time, the enable signal is changed to a zero state to turn off the transistors
306
and
308
. The timer
314
must provide the enable signal for a sufficient predetermined time for the data to load and latch before turning off the transistors
306
and
308
.
The pulse width of the enable signal in the conventional memory system must be sufficiently long for the circuit to latch. However, because the power signal is noisy during power up, the circuit may not sufficiently latched before the enable signal is disabled.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a data latch signal that is timing independent and draws low power.
The present invention provides a self-latching data circuit that comprises first and second memory cells. The self-latching data circuit also includes first and second n-channel field effect transistors (NFETs) coupled to the respective first and second memory cells for providing contents therein, in response to an enable signal having a first state applied to a gate of each of the first and second NFETs. A third NFET couples the first NFET to a first data node. A fourth NFET couples the second NFET to a second data node. The first data node is coupled to a gate of the fourth NFET. The second data node is coupled to the gate of the third NFET. A first p-channel field effect transistor (PFET) couples a voltage signal to the first data node in response to the enable signal having the first state being applied to a gate of the first PFET. A second PFET couples the voltage signal to the second data node in response to the enable signal having the first state being applied to a gate thereof. A third PFET couples the voltage signal to the first data node in response to the second data node. A fourth PFET couples the voltage signal to the second data node in response to the first data node.
The present invention also provides a circuit that comprises first and second subcircuits. The first subcircuit includes a first transistor of a first type having a drain coupled to the power signal line. A first transistor of a second type has a drain coupled to the source of the first transistor of the first type to form a first data node, has a gate coupled to the gate of the first transistor of the first type to form the first feedback node and has a source. A second transistor of the first type has a drain coupled to the power signal line, has a gate coupled to an enable signal line and the source coupled to the first data node. A second transistor of the second type has a drain coupled to the source of the first transistor of the second type, a gate coupled to the enable signal line and a source coupled to a first input node. The second subcircuit has a third transistor of a first type having a drain coupled to the power signal line. A third transistor of the second type has a drain coupled to the source of the third transistor of the first type to form a second data node and coupled to the first feedback node, a gate coupled to the gate of the third transistor of the second type to form a second feedback node and coupled to the first data node, and a source. A fourth transistor of the second type has a drain coupled to the power signal line, a gate coupled to the enable line and a source coupled to the second data node. A fourth transistor of the second type has a drain coupled to the source of the third transistor of the second type, a gate coupled to the enable signal line, and a source coupled to the second input node. The first and second input nodes may be coupled to first and second memory cells.
REFERENCES:
patent: 4644185 (1987-02-01), Todd
patent: 5640115 (1997-06-01), Halepete et al.
patent: 5929659 (1999-07-01), Pantelakis et al.
patent: 6107853 (2000-08-01), Nikolić et al.
patent: 6222765 (2001-04-01), Nojima
Gray Cary Ware & Freidenrich LLP
Mai Son
Silicon Storage Technology, Inc.
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